| An approach for input data compaction in the testing of circuits using scan and partial scan has recently been developed based on the reseeding of multi-polynomial Linear Feedback Shift Registers (LFSRs). This thesis explores further compression of test data through the grouping of closely related vectors into clusters and extracting both common information, in a form compatible with the reseeding method, and individual information for the component vectors.;Two greedy algorithms for finding these clusters are described, the first trying to form the largest groupings while the second trying to make the most advantageous mergers at each step. In addition, several schemes of storing and decoding the information needed for individual vectors are presented, some of which use memories in the form of stacks or caches to take advantage of the distribution of this data. Aside from the LFSR, some counters and the memory, little additional hardware is required. The solutions offer a range of trade-offs between test length, hardware complexity and test data storage.;Results are given for experiments carried out on ISCAS-89 benchmark circuits and on a set of industrial circuits contrasting the performances of the algorithms and the requirements of the different methods of storage. Considerable improvements over reseeding are demonstrated, more so for the industrial circuits which are inherently hard to test. |
