Routability prediction for field programmable gate arrays with hierarchical interconnection structures

Within the last dozen years, Field-Programmable Gate Arrays (FPGAs) have emerged as a cost-effective means of implementing logic circuits as a customized VLSI chip due to their user-programmability. However, FPGAs are still relatively new and require more architectural research in order to improve the performance of designs implemented on them.;One area of particular importance is the design of an FPGA's routing architecture. This thesis examines a new hierarchical routing architecture for FPGAs and a statistical model to predict the routability of such FPGAs, referred to as hierarchical FPGAs, or HFPGAs. We also examine the performance of HFPGAs compared to standard Symmetrical FPGAs, and various effects the routing architecture has on routability. Experimental results show that the HFPGA architecture requires less routing resources than those required in a symmetrical FPGA architecture.