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Reconfigurable micro-grain VLSI arrays: Architectures and algorithms

Posted on:1996-10-03Degree:Ph.DType:Thesis
University:The Pennsylvania State UniversityCandidate:Bajwa, Raminder SinghFull Text:PDF
GTID:2468390014487947Subject:Computer Science
Abstract/Summary:
SIMD architectures such as the Illiac-IV and the Connection Machine series have shown tremendous performance for tasks where large amounts of relatively simple processing have to be performed on a large data set and the operations being performed are regular and can be applied to small units of data. With the increasing proliferation of desktop computing the question arises: How can one provide users of such systems with hardware that gives supercomputer performance, for a restricted span of applications, for a fraction of the cost? A growing number of users regularly perform computationally intensive image and signal processing tasks as part of their work. A cost-effective computational platform that can augment generic desktop machines with exceptional performance for these applications would be quite attractive.;This thesis demonstrates a fine grain architecture, which leverages VLSI technology and incorporates reconfigurable features, which provides high performance at a reasonable price. A family of fine grain architectures is presented along with a performance analysis for a sample of image and signal processing asks. Algorithms are developed for such systems. A hardware prototype, along with the concomitant software, of the SIMD architecture has been constructed and performs to expectations. It also proves that such architectures can be constructed economically. The range of algorithms includes image and signal processing, speech processing, molecular biology, and fluid dynamics demonstrating the versatility of the architecture. The prototype is called MGAP-1 for first generation Micro Grain Array Processor.;To show that the MGAP approach is better than, or at least as good as, a workstation's an analysis comparing the performance of the second generation MGAP with the DEC Alpha workstation is presented for low level arithmetic operations highlighting the effect of a wide memory to processor path.;Furthermore, based on an analysis of program behavior on the MGAP-1, it is shown that certain code structures tend to repeat and so the hardware can be modified to improve performance further.
Keywords/Search Tags:Performance, Architectures, Grain, Image and signal processing
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