Clock routing for low power

Clock is an essential component of any synchronous digital circuit. Due to its high switching activity and large capacitive loading, the clock is a significant source of power consumption. This thesis considers the problem of clock tree routing with the objective of minimizing the power consumption of the clock tree subject to skew constraints. In order to achieve this objective, two methods are investigated; tolerable skew clock routing and gated clock routing.; The tolerable skew clock routing allows clock skew among clock sinks as long as this does not violate the timing constraints of the system. This method results in lower routing area (capacitive loading) for the clock tree compared to the conventional zero skew clock routing, thereby reducing the power consumption. The key contribution of my solution method is the Edge Based Formulation (EBF) which casts the clock routing problem as a mathematical programming problem where the variables are the edge lengths of the tree, instead of the coordinates of the Steiner points. The EBF simplifies geometric optimization tasks in the Manhattan space. The effectiveness of the method is demonstrated through examples and experimental results.; The clock gating is a method of shutting off the clock inputs to the circuit modules when they are idle. The proposed gated clock routing method shuts off the clock at the internal nodes of the clock tree, thereby saving power on the clock subtree in addition to the power in the idle modules. This work is best applied to microprocessor chip design where the statistics and the behavior of the instructions are known. This information, along with the locations of the clock sinks, determines the routing of the clock tree that will minimize the power consumption.; The final part of the thesis describes a method for power and ground (p/g) network design for high speed CMOS chips with multiple p/g pads. The objective is to distribute the total ground bounce in the chip uniformly among the p/g pads such that each pad experiences almost the same amount of ground bounce while the total routing area for the p/g network is minimized. This method addresses a new problem domain in ground bounce control which conventional methods have often neglected.