Low-phase-noise, low-timing-jitter design techniques for delay cell based VCOs and frequency synthesizers

Timing jitter and phase noise are important design considerations in almost every type of communications system. Yet the desire for high levels of integration in many communications applications works against the minimization of these, and other, sources of timing error--especially for systems which employ a phase-locked loop for timing recovery or frequency synthesis. With the growing interest in high-integration implementations there has been an increasing demand for fully-monolithic, on-chip VCO and synthesizer designs. Delay cell based VCOs (ring-oscillators) and delay chains have been used successfully in many applications, but thermal-noise induced timing jitter and phase noise have limited their applicability to some systems. Of particular interest are RF frequency synthesizers, used in wireless communications transceivers, which have stringent requirements on oscillator phase noise but stand to benefit greatly from a highly integrated solution.; In this thesis the fundamental performance limits of ring oscillator VCOs and delay buffers are investigated. The effects of thermal noise in transistors on timing jitter and phase noise in such these circuits is explored, with particular emphasis on source-coupled differential resistively-loaded CMOS delay cell implementations. The relationship between delay element design parameters and the inherent thermal noise-induced jitter of the generated waveform are analyzed. These results are compared with simulated results from a Monte-carlo analysis and experimental results for a ring-oscillator test array fabricated in 0.6{dollar}mu{dollar}m CMOS technology with good agreement. The implications of this analysis for the design of low-timing-jitter and low-phase-noise buffers, VCOs and PLLs using inverter delay cells are described.; The analysis shows that timing jitter is inversely proportional to the square root of the capacitance at the output of each inverter, and inversely proportional to the gate-source bias voltage above threshold of the source-coupled devices in the balanced state. Furthermore, these dependencies imply an inverse relationship between jitter and power consumption for an oscillator with a fixed output period. Phase noise and timing jitter are predicted to improve at a rate of 10 dB per decade increase in power consumption (and area). For a given output frequency and power consumption an oscillator with a minimum number of delay cell elements is desired to minimize timing jitter. These conclusions, as well as many practical considerations for ring-oscillator VCO design are described. The results show that delay cell based VCOs and synthesizers have significant potential for at least some range of RF frequency synthesizer applications.