| The MOSFET critical dimensions shrink more rapidly than its applied voltage for state-of-the-art IC technology. Hence, the maximum electric field along the channel becomes larger in almost every technology generation, affecting device reliability. Therefore, attention should be paid not only to the modeling of the device degradation, but also to the physical mechanisms that lie behind it to find effective ways of improving hot carrier lifetime without degrading device performance.; In this thesis, the impact of post-metallization deuterium anneal on different degradation mechanisms will first be presented. From experiments, it is found that deuterium anneal can effectively suppress the interface state generation from hot electron bombardment, but is less effective in reducing other degradation mechanisms, such as electron trapping, hole trapping, or interface state generation by electron-hole recombination.; Under accelerated testing conditions, the worst-case bias condition for hot carrier degradation in nMOSFETs changes from Ib,peak (peak substrate current condition) to Vg = Vd, as the effective channel length becomes smaller. The degradation mechanism is the same at both bias conditions. The switch of the worst-case stress condition can be understood by considering the shape of the substrate current curve and the location of the current trajectory. At the operating voltage, the worst-case stress condition is found to be Ib,peak.; In 0.25-mum and 0.1-mum technologies, pMOSFETs show a different degradation behavior. For 0.25-mum technology, ac stress causes more degradation under accelerated testing conditions than does any dc bias condition, but at the operating voltage, biasing at Ib,peak is still the worst-case stress condition. At all bias conditions, the device degradation is primarily due to interface state generation, and more than one interface state generation mechanisms are suggested by the experimental data. As the applied voltage is lowered, the dominant interface state generation mechanism changes, and the worst-case stress condition shifts to I b,peak. For ultrathin oxide 0.1-mum technology, the worst-case stress condition is at Vg = Vd at both the stress and the operating voltage, and hole trapping is the primary degradation mechanism.; High performance integrated circuits can operate at temperatures as high as 100°C. Hot carrier degradation at an elevated temperature (T = 100°C) is examined. At the operating voltage, the worst-case stress condition for both nMOSFETs and pMOSFETs at 100°C is Vg = Vd. The current flows closer to the Si/SiO 2 interface at 100°C, which makes the worst-case stress condition occur at Vg = Vd for nMOSFETs. In pMOSFETs, the hot-hole injection current becomes larger as the temperature increases. The hole trapping and interface state generation make Vg = Vd the worst-case stress condition for pMOSFETs at 100°C. Comparing the room temperature and the 100°C results, the accelerated test is recommended to be performed at the expected circuit operating temperature.; Reliability simulation of a 51-stage ring-oscillator was performed. The circuit lifetime improvement due to D2 anneal can be well estimated by the device dc lifetime improvement data. |
