| In the era of Deep Sub-Micron technologies the impact of interconnect induced effects is becoming more and more important in the correct functionality and performances of complex VLSI System-on-Chip designs. In the traditional approach interconnect effects are taken into account during logic synthesis by means of the wireload model. However, for technologies of 25μm and below, the interconnect capacitance dominates the gate capacitance and delay estimations based on fanout can be highly inaccurate. Therefore, delay optimization in logic synthesis founded on wireloads does not correlate with post-layout analysis. Changes in the grate level netlist during physical design are limited, and if performance constraints cannot be satisfied after layout generation, then the netlist must be resynthesized and the overall process which includes logic synthesis, placement and routing goes through several iterations with no guarantee to converge and meet the performance constraints.; In order to achieve a fast timing closure, more accurate interconnect models must be available during the synthesis phase, but interconnect geometries which are crucial for a precise evaluation of the distributed RC effects are not known prior to layout. Therefore, a more effective integration between logic synthesis and physical design is necessary to obtain a fast timing convergence, thus significantly improving the development cycle and time-to-market of modern VLSI systems. Moreover, cell area minimization no longer correlates with total block area minimization, since in Deep Sub-Micron technologies also the wiring area must be considered in order to synthesize circuits which not only satisfy timing constraints, but that are also routable within fixed die size constraints. Hence, wiring congestion is another limiting factor which must be considered during the logic synthesis phase. Wiring congestion directly impacts on performances, and by controlling congestion, also wirelength and path delays are minimized.; This thesis describes a novel approach which incorporates wiring congestion within logic synthesis. In particular, a congestion-aware technology mapping algorithm is presented, where by using the physical information obtained from the initial placement of the decom posed netlist consisting of base functions, a mapped gate level netlist with improved routability is obtained. The trade-offs between cell area and congestion minimization are explored, and a methodology for congestion minimization at the logic synthesis level is proposed. This methodology can be efficiently integrated within the ASIC design flow. Results showing the effectiveness of our approach are presented and discussed in detail. |
