| The MOSFET critical dimension shrinks more rapidly than its applied voltage for state-of-the-art IC technology. Aggressive scaling of the oxide thickness is necessary for enhancing circuits speed, thereby offsetting the disadvantage of supply voltage reduction. The electric field in the gate oxide is expected to increase and this may pose a potential reliability concern. The time-dependent dielectric breakdown (TDDB) is a major cause of failure in small dimension devices. A good understanding of the physical effects resulting from the application of large electric fields to thin oxides is therefore necessary.; In this thesis, the impact of post-metallization deuterium anneal on oxide reliability will be presented. From experiments, it is found that deuterium anneal can effectively suppress the interface state generation from hot electron bombardment, but has no effects in improving the oxide reliability, such as time-to-breakdown or stress-induced leakage current. Therefore, this finding suggests that a model for gate oxide breakdown that involves release of interfacial hydrogen may not be accurate.; Gate oxide failure is one of the failure mechanisms during an electrostatic discharge (ESD) event. For thick oxide bias under high field, the time-to-breakdown is expected to follow the 1/E model. However, for ultrathin oxide stressed under low voltage, the degradation and breakdown are determined by stress voltage instead of electric field. Thus, the damage of ultrathin gate oxides under ESD stress conditions needs to be reexamined. In this thesis, time-to-breakdown of ultrathin gate oxides is investigated down to the nanosecond time regime. The 1/E model best fits the time-to-breakdown data. Latent damage is also examined, and it is seen that the trap generation rate is a function of stress pulse width for nanosecond and microsecond stress pulses. In addition, thermal simulation has been carried out to study the temperature rise during ESD events. The pulse-width dependent trap generation rate has been attributed to time-dependent self-heating in the oxide. Thus, dc data should not be used to predict the degradation rate under ESD-type stress conditions.; For ultrathin oxides, a new type of failure mode, soft breakdown, has been observed. The characteristics of this kind of failure are often identified by a large increase of gate signal noise level. It has been proposed that there is a threshold power that divides soft and hard breakdown. In this thesis, time-to-breakdown of ultrathin gate oxide is tested, and the power dissipation after breakdown is obtained. Based on the critical power value that separates the soft and hard breakdown, thermal simulation is done using finite element analysis. The effects of interfacial thermal resistance and nanoscale heat conduction are included in the thermal model. The simulation results show that the diameter of leakage path is between 0.1 and 0.5 nm in order to raise the temperature close to glass transition temperature of SiO2. At this temperature, the structure change of SiO2 could leads to the breakdown of oxide. |
