A configurable hardware/software system for design rule checking

Design rule checking is an important step in very large-scale integrated circuit (VLSI) design. The circuit layout is checked against a set of geometric restrictions, namely design rules to ensure a margin of safety in the fabrication process. The time spent on design rule checking contributes significantly to the time to tape out and the checking time is expected to increase as the complexity of the circuit increases. In the past, some efforts were proposed to accelerate the design rule checking problem through custom hardware, but these efforts were hobbled by the fact that it is often impractical to build a different rule checking hardware each time the design rule set changes.; This thesis presents a configurable hardware approach to design rule checking. Although design rules vary between different fabrication processes and change over time, their intrinsic similarity makes it possible to build a general scalable hardware system based on scanline algorithm. Through processing the design rule specific information in the configurable hardware, the system can garner impressive speedups over software approach while retaining the flexibility to adapt to different design rule sets. The hardware system, implemented on Xilinx 4013e FPGAs and prototyped on Pamette board, achieves a clock rate of 33Mhz and a performance speedup of 25X over the software approach.; For a standalone design rule checker that handles raw layout files, however, the above hardware system is not sufficient. The layout data need to be extracted and converted to the format used in hardware scanline processing. In the case of hierarchical design rule checking, cell interaction information need to be extracted and checked as well. It is thus necessary to build a software front end to perform the layout data preprocessing. The software uses quad list quad tree as the basic data structure and halo algorithm for hierarchical layout analysis. The rule checking of each individual cell is cast in the hardware while the preprocessing steps and the cell interaction checking are done in software. Counting both the software and hardware runtime and communication cost between software and hardware, our standalone design rule checker achieves a 5–50X speedup over the commercial software.; The run time analysis of each individual step in the above approach shows that software cell interaction checking takes too much time. Because of this, the initial hardware, which was only capable of handling flat layout data, is modified to check both the cell internal geometry and the cell interaction. Through keeping track of the “environment” information for each cell instance and employ proper context-switching techniques, the hardware is capable of checking multiple cell instances simultaneously. This final approach has further improved the performance of the overall system and has achieved a 5–100X speedup over the commercial software.