| In today's leading-edge semiconductor technologies, it is increasingly difficult for IC designers to achieve sufficient improvements of performance, power and area metrics in their next-generation products. One root cause of this difficulty is the increased margins that are used in the design process to guardband for (i) variability and aging, as well as (ii) analysis inaccuracies. Currently, these margins incur huge costs to design companies, because the benefits by deploying the next technology node is only approximately 20% in circuit performance, power and density. To reduce margins, fast and accurate pathfinding of architecture, technology and constraints choices are essential. A second root cause is the high cost (and, therefore, limited supply) of electronic design automation tool licenses, accompanied by the lack of any systematic methodology to optimize the use of available tools within long-duration, highly iterative design processes. This constrains designers to perform only limited design-space exploration, so as to keep within limits on design infrastructure cost and design turnaround time. This thesis presents new techniques to reduce guardbands in optimization loops in the IC design process by using fast and accurate learning-based models. These techniques can be grouped into three main thrusts: (i) productivity through improved design- and implementation-space exploration; (ii) improved accuracy of electrical modeling and enablement of auxiliary physical design optimizations; and (iii) design power, energy, management and cost optimizations. In the productivity through improved design- and implementation-space exploration thrust, this thesis presents four applications of learning-based models for accurate prediction of area, power, timing and routability. To enable area and power estimation of Networks-on- Chip routers, so that architecture-level (RTL-level) design-space exploration can be efficient performed, this thesis presents an open-source tool, ORION3.0, that has been released on the web. In the improved accuracy of electrical modeling and enablement of auxiliary physical design optimizations thrust, this thesis presents new methodologies to perform high-dimensional learning-based modeling of delay, transition time and slack in timing paths. A methodology to develop accurate models of post-routing optimization of signal delays at multiple signoff corners, so as to enable a new optimization of clock skew variation across corners is also described. In the design power, energy, management and cost optimizations thrust, this thesis presents three distinct works that directly benefit leading-edge SoC design companies. The first work describes a new analytic three-dimensional placement tool using a new objective function that achieves significant wirelength and power reduction relative to two-dimensional implementations. The second work provides two mixed integer-linear programs for optimal multi-project, multi-resource allocation with task precedence and resource co-constraints for IC design management and cost reduction. The third work presents a maximum-value, reliability-constrained overdrive frequencies problem that guarantees prescribed lower bounds on acceptable performance and acceptable throughput in multicore systems, without exceeding prescribed lifetime budget for any core. |
