High performance, high speed VLSI architectures for wireless communication applications

This thesis is devoted to high performance and high speed VLSI algorithm and architecture design of wireless transceiver building blocks which perform the two major classes of digital signal processing: adaptive least square filtering and turbo decoding.; Hybrid Annihilation Transformation (HAT) for pipelining QR decomposition (QRD) based least square adaptive filters has been developed. HAT provides a unified framework for the derivation of high-speed VLSI architectures of QRD-RLS, QRD-LSL, and QRD multi-channel LSL adaptive filters. In addition, Generalized annihilation reordering transformation has been proposed to show that M filtering errors can be obtained as smoothed filtering results in one clock cycle where M is pipelining or parallel processing level. The proposed transformations introduce no performance degradation no matter how deep the filter is pipelined. It allows a linear throughput speedup by linear increase in hardware complexity.; Turbo decoding metrics aided short CRC codes error detection algorithm has been developed and applied to short frame terminated turbo codes, novel efficient tail-biting turbo codes and CRC embedded turbo codes to realize adaptive decoding and accommodate ARQ protocols. Significant coding gains can be achieved by actually increasing the transmission rate with negligible increase in power consumption.; In addition to strategies on reducing the complexity of general block turbo decoders, a novel robust sub-optimal decoding algorithm for decoding (32,21)2 (extended BCH code over GF(2 5)) block turbo codes has been proposed. The algorithm achieves 10 −6 bit error rate at SNR 2.4 dB for AWGN channels, which is the best performance among all 2-D turbo product codes. Top level fully parallel decoding architecture and lower level high speed implementation strategies such as critical path reduction using lookahead techniques and fast finite field operations have been developed. An up to 85M bits/s decoding throughput can be achieved by using 0.18 μm, 1.5V CMOS technology.; Iterative decoding of concatenated space-time trellis codes and convolutional codes has been studied as an initial work for further research. Extra coding gains in addition to the diversity advantage is shown to have been achieved for certain space-time trellis codes transmitted over both quasi-static and fast flat fading channels.