| Power consumption is becoming an increasingly important problem in contemporary computer systems in the following two respects: (i) For general purpose processors, the traditional methods to obtain higher processor performance by integrating more and more transistors are impeded by the increased power consumption. (ii) For embedded processors, power is one of the primary design constraints other than the performance and area, for longer battery life and portability. The problem of reducing processor power consumption has been studied at circuit level extensively before, and now it is actively studied by architects and compiler designers.; This thesis studies processor power consumption from the following three perspectives: (i) Register spilling. For performance reason people favor schedules that balance instruction parallelism and register allocation, that is why in the past studies focused on integrated register allocation and instruction scheduling approaches. This thesis argues that in today's out-of-order issue processors, register allocation should take precedence over instruction scheduling to minimize energy consumption for the following two reasons: (1) The false dependencies introduced by register allocation may not have performance penalty since the underlying hardware can eliminate them at run-time. (2) A schedule with fewer register spills has the additional benefit of reduced power consumption. (ii) Functional unit usage in software-pipelined loops. Software pipelining can effectively speedup loop execution by overlapping execution of different iterations. Initiation interval, referred to as II, is the primary performance indicator of software-pipelined loops and previous works strived for minimum II under the given resource constraint. This thesis shows, performance-optimal schedules differ in their power consumption and there is a schedule within the performance-optimal ones that consumes minimum amount of power. Further, it formulates the problem of generating power-minimum software-pipelined schedule while keeping performance-optimality as an integer linear programming problem, and evaluates the power reduction in comparison with that generated by MIPSpro compiler. (iii) Memory accesses due to cache misses. Cache access consumes much less power than memory access thus enhancing cache locality is an effective approach to reduce power. (Abstract shortened by UMI.)... |
