An investigation of the simulation performance of Verilog for large circuits

Scope and method of study. The purpose of this research is to find a method to estimate the simulation time for a large digital circuit. A sample circuit is simulated and used to predict the simulation time for similar designs.; Findings and conclusions. The prediction of the simulation time can be extended to any circuit by finding a reference circuit. The simulation time of a shift register reference circuit has been determined as a function of the number of bits in the circuit and the number of clock cycles simulated. The reference circuit simulation time serves as a lower bound for the simulation time of more complex circuits.