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On the burstiness of TCP traffic at backbone routers

Posted on:2006-05-20Degree:Ph.DType:Thesis
University:University of Southern CaliforniaCandidate:Shah, KhushbuFull Text:PDF
GTID:2458390008459305Subject:Engineering
Abstract/Summary:
The performance of tier-1 networks is typically measured in terms of delay and packet loss. These metrics are closely related; delay occurs when the packet arrival rate surpasses the out-going link speed while packet losses occur when this mismatch is extreme and/or persistent. Basic network models show that in order to keep delay low, the average packet arrival rate must be substantially lower than the link bit-rate. However, average packet arrival rate less than the link bit-rate does not guarantee low queuing delay. Rather, it is the extremes in the packet arrival rate that produce delay and losses.; First, this thesis investigates these extremes in packet arrival rate. In particular, the causes of the tail of the distribution of the number of packet and byte arrivals at backbone routers are examined. One possible cause is that sometimes there are a large number of active connections resulting in a large number of arrivals in a short period of time. Another possibility is that the tail is due to one or a few very fast connections. By examining arrivals from several backbone links, we find that the tail is neither strictly from many users nor strictly from fast connections. This part concludes that there are two major causes of bursty network traffic: the number of connections sending data is bursty and the bit-rates are bursty. The former is well understood and is related to the long tailed file distribution. On the other hand, bit-rates have received less attention. Hence, second, this thesis examines bit-rates at short time-scales as observed along two backbone links. We use chip-rate to quantify the short-term bit-rate. We define the chip-rate of a packet at a time-scale T to be the maximum number of bits sent over any time interval of duration T that contains the packet, divided by T. Three areas are addressed. First, we examine which flows are responsible for sending packets at high chip-rates. Second, we consider the impact of high chip-rates. Third, we examine the causes of the high chip-rates.
Keywords/Search Tags:Packet, High chip-rates, Backbone, Delay
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