A power system protection scheme combining impedance measurement and travelling waves: Software and hardware implementation

For the stability of the electrical network, it is important to clear faults on high voltage transmission lines quickly with the aid of a high-speed protection system. The conventional method of fault detection is mainly based on impedance measurement techniques. Under fault conditions the measured impedance is proportional to the distance to the fault from the relay location. To calculate the impedance, the fundamental frequency components of the voltage and current signals have to be extracted. The filtering involved in this process has an inherent delay. Any attempt to increase fault detection speed can affect the accuracy of the distance estimation and hence the reliability of the protection scheme.; Fault generated transients or travelling wave signals provide the very first information about a possible disturbance on the line and hence can be used to detect faults very quickly. Ultra-high-speed distance protection schemes based on fault initiated travelling waves measure the distance to the fault using the time taken for a wave to travel from the relaying point to the fault and back. However, travelling wave based protection schemes have reliability issues and have not been well accepted by relay engineers despite their fast fault detection capabilities.; In this thesis, a hybrid protection scheme is proposed which uses positive features of both travelling wave algorithm and impedance measurement technique in a single relay. The travelling wave information is used to achieve fast fault detection speeds while the impedance measurement is used to improve the reliability of the overall protection scheme. The thesis also investigates the possibility of accelerating the zone 2 protection of an impedance relay depending on the travelling wave information. The proposed algorithm has been verified through simulations of a practical three phase power system. The relaying functions have been tested using a laboratory prototype implemented on a Texas Instruments digital signal processor. The results indicate that the fault detection speed is improved while maintaining a high reliability level.