| Flash memory has to be the right choice of the non-volatile semiconductor memory market for decades, due to its well balanced functionality and cost. It has kept scaling down aggressively. One of the most crucial challenges for further scaling is the reduction of the tunnel dielectric thickness without sacrificing the 10-year retention, and other reliability issues. This dissertation study is focused on the tunnel dielectrics for scaled, high performance flash memory technology.; A high-k dielectric is attractive for long retention of flash memory due to its larger physical thickness, and fast programming/erasing speed due to the lower barrier height. In this thesis work, a Molecular-Atomic Deposition (MAD) technique has been developed to synthesize trap-free Si3N 4, and high quality HfO2 and HfON. Intensive effort has been devoted to construct the MAD machine, reduce the contamination level, and develop the processes of dielectric deposition. The optimized MAD Si 3N4 demonstrates almost stoichiometric composition, and trap-free characteristic. It also shows immunity to stress induced leakage current (SILC). The MAD HfO2 and HfON exhibit very low trap densities through various characterizations.; The MAD trap-free Si3N4 has been studied as the tunnel dielectric for NOR type flash memory application. The MNSFET with MAD Si3N4 as the gate dielectric demonstrates orders higher injection efficiencies for hot electrons and hot holes, due to the reduced barrier heights for both carriers. The MNNNS memory cell shows aggressively scaled dielectric thickness with fair retention property, owing to the higher k-value of silicon nitride.; The concept of crested tunnel barrier has been investigated in detail for NAND type of flash memory application. Careful barrier engineering design, considering the barrier heights, dielectric constants, thickness ratios of the constituent tunnel barriers, and the work function of the electrode, has proven necessary to realize sharper I-V slope than that of SiO2. A one-side Al/(HfON-Si3N4)/p+-Si crested barrier has been fabricated, and exhibits expected steep I-V slope. In addition, we have fabricated a MONOS test cell with the above mentioned crested tunnel barrier, and found that it exhibited faster programming speed and longer retention than the control cell with a SiO2 tunnel barrier. |
