| This thesis describes extensive process module development, which enabled the demonstration of well behaved, L[g] = 300 nm, III-V MOSFETs with I[d,sat] = 243 mA/mm and excellent sub-threshold performance (sub-V[t] slope = 85 mV/dec, I[sd,leak] = 1.5x10[-4] mA/mm, DIBL = 90 mV/V). Progress was made in five main areas; 1) material design, 2) ohmic contacts to shallow III-V MOSFET structures, 3) device isolation using ion implantation, 4) oxide passivation and 5) III-V MOSFET device architecture development. 1) Pre-MOSFET material was used to develop the active layer design. A wide band-gap AlAs/GaAs superlattice/AlGaAs buffer was found to improve channel confinement. This enhanced electron mobility from 1535 to 3950 cm[2]/Vs, with the potential for increased I[d,sat]. Pre-MOSFET material was also used to optimise channel composition and delta-doping density. 2) Various oxide etch, metallisation and treatment schemes were investigated for the realisation of ohmic contacts to shallow III-V MOSFET material. The lowest Rc achieved was 0.62 O.mm 3) Mesa isolation is not suitable for III-V MOSFETs, so an alternative ion implantation isolation technique was developed. Oxygen ion implantation isolation of III-V heterostructures is widely used, but isolation of shallow structures is novel. Isolation of pre-MOSFET material gave R[sh] = 10GO/sq. 4) Oxide passivation processes were developed to maximise carrier concentration and hence I[d,sat]. Pre-passivation III-V MOSFET R[sh] > 1000 O/sQ was typically measured, but after passivation, using a ICPCVD Si[3]N[4], R[sh] reduced to ≈ 400 O/sq. Experiments indicated that the physical passivation mechanism was related to the high density ICP N[2] plasma. 5) A novel self-aligned gate process was developed to reduce access resistance and improve I[d,sat]. This process did not result in the demonstration of working devices, but with further development should enable self-aligned devices to be realised. |
