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Transparent memory hierarchy compression and migration

Posted on:2009-08-14Degree:Ph.DType:Thesis
University:Northwestern UniversityCandidate:Yang, LeiFull Text:PDF
GTID:2448390005451224Subject:Engineering
Abstract/Summary:
Embedded systems are ubiquitous. Although many aspects of embedded system design and synthesis have received significant research attention, comparatively less attention has been given to new ideas in memory hierarchy design. This dissertation presents several new operating system and architecture techniques that use elements of the virtual and physical memory system to improve the functionality, power consumption, and performance of embedded systems such as multimedia devices and wireless sensor network nodes. In particular, the techniques presented in this dissertation explore the use of software and hardware compression of physical and virtual memory to improve performance and functionality of uniprocessor and multiprocessor systems.;We describe an operating system controlled, on-line memory compression framework for embedded systems that support virtual memory but have tight physical RAM constraints. We present a new software-based memory compression algorithm and a method of adaptively managing the uncompressed and compressed memory regions during application execution. We also describe the use of software on-line memory compression in embedded systems that do not support virtual memory, e.g., wireless sensor network nodes. Specifically, we focus on a new compression algorithm that is developed for compressing sensor data.;We present a hardware-based, adaptive cache and memory link compression framework to improve the performance of applications with large working data sets. We propose efficient organization scheme to manage compressed cache lines, and present detailed hardware design and synthesis results of the area and performance overheads of the required compression and decompression hardware. In addition, we present a cooperative cache compression and migration technique to improve in chip multiprocessor throughput without increasing area, or to reduce area without degrading throughput. We propose an adaptive control policy integrating the two techniques and permitting run-time adaptation to workload.
Keywords/Search Tags:Memory, Compression, Embedded systems
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