Utilisation de la reconfiguration dynamique des FPGA pour le controle precis et exact des delais dans les convertisseurs temps a numerique

Time interval measurement is important in various scientific and engineering applications. A Time-to-Digital Converter (TDC) is an integrated circuit allowing measurement of time intervals with resolutions and precisions down to a picosecond. Until the last decade or so, these circuits were implemented exclusively as application specific integrated circuits (ASIC), but since then, various implementations targeting field-programmable gate arrays (FPGA) have been proposed. While these implementations still deliver reduced performances in terms of resolution and precision, there is a growing interest within the scientific community to reduce this gap. Indeed, with the dazzling progress of the FPGA technology over the past decade, both in terms of logic density and operation frequency, it is becoming a implementation target of choice for an ever growing range of circuit and systems. Two key benefits from such implementations are considerably reduced development times and non-recurring costs. It is therefore in this context that this work is focused on the FPGA implementation of time-to-digital converters.;In order to address the limitation imposed by minimal delays, this work proposes an approach based on the fine and precise adjustment of delays. The novelty of this approach resides in its ability to exploit two characteristics of FPGAs, namely the richness of the programmable interconnections fabric and the possibility to reconfigure the circuit dynamically. The latter, dynamic reconfiguration, is supported by some FPGAs and enables the user to reconfigure partially the circuit while in operation. As there exist a considerable amount of possible routes between two points of an FPGA, dynamic reconfiguration of the programmable interconnection fabric potentially enables delay adjustments with unprecedented resolutions. Indeed, our results show that the proposed delay line enables adjustments with a resolution of 1ps on a range that can span over 2,5ns.;On the basis of these fine resolution delay lines, a novel TDC architecture is proposed. Relying on the utilization of multiple parallel delay lines, the resolution achievable is now limited by the ability to adjust delay differences, instead of the previous limitation imposed by minimal delays. Therefore, such an architecture can potentially deliver resolutions lower than those found in state-of-the-art FPGA implementations. However, fine delay adjustment is itself insufficient to achieve the desired goal, and a calibration process enabling precise adjustment is also proposed. Delays are affected by both temperature and fabrication process variations of the chip. In order to enable precise delay adjustment, the proposed calibration take into account these variations, as well as clock skew. Using the proposed methodology, a TDC featuring 50ps resolution and 48ps precision was obtained. Moreover, results show that the methodology can be used to achieve resolutions as fine as 10ps. To our knowledge, to this day, such resolution is the lowest ever reported in the literature for an FPGA implementation.;Our approach based on fine and precise delay adjustment is also applied to a preexisting TDC architecture based on the Vernier method with two oscillators. With this architecture, the achievable resolution corresponds to the period difference between the two oscillators. As our methodology enables precise period adjustment of a ring oscillator, the proposed implementation can deliver considerable resolution improvement when compared to those proposed in the literature. Indeed, our results show that resolutions below 5ps can be obtained. However, because of the instability of the oscillators, precision at such resolutions exceeds 100ps. Nevertheless, precisions of 25ps can be obtained at equivalent resolutions. Moreover, when compared to static approaches proposed in the literature, our approach using dynamic reconfiguration is remarkable as it takes into account both temperature and fabrication process variations.;While ASIC implementations of TDC can enable resolutions neighbouring a single picosecond, most recent FPGA implementations are still limited to a few tens of picoseconds. As the implementation of a TDC is closely related to the notion of delay, FPGAs are handicapped both by the irregularity of interconnection delays, and increased minimal delays. Therefore, to this day, the most successful FPGA implementations that have been proposed in the literature rely on architectures allowing to take advantage of dedicated interconnection structures, such as the carry-chain used in arithmetic circuits. Indeed, these dedicated interconnection structures provide both reduced delays and increased interconnection delay regularity. However, the resolution achievable with such architecture is limited by the minimal delays available on the circuit, which are substantially more important on an FPGA than on an ASIC. Nevertheless, this architecture directly benefits from newer generations of FPGAs, produced with fabrication processes that enable reduced minimal delay.