Low-cost and efficient architectural support for correctness and performance debugging

Thesis statement. Efficient architectural support for debugging correctness and performance of programs can be achieved at low cost and minimal performance overheads.;Moore's law has enabled rapid advances in computer hardware. There are billions of transistors inside modern day processors. This increasingly powerful hardware has been exploited by increasingly complex software. As a result, software is prone to a variety of bugs---some of which have even become security exploits. Over the past years, there have been several incidents related to program bugs and their consequences have ranged from monetary losses to costing human lives. Correctness debugging ensures that a program does not exhibit any unintended behavior during runtime.;While there can be no second thoughts on whether a program should be correct, ensuring good performance of software is equally important. Performance debugging mechanisms are aimed at locating performance bottlenecks and helping to improve program runtime. With multi-core processors becoming rapidly popular in today's market, the need to boost performance is even higher. These multi-core processors have an added value only if the software vendors can take full advantage of the available cores. Hence, scalable program performance is important in these platforms.;Prior works have studied either software-based or hardware-based solutions to address program correctness and performance. Software-based solutions are low-cost and flexible but usually incur very high performance overheads. Hardware-based solutions are efficient with low performance overheads but are usually expensive and inflexible. If we can get the best of both worlds by leveraging the flexibility and low-cost from software and efficiency from hardware, that would make debugging solutions more attractive for software developers.;In this dissertation, three novel techniques that provide hardware support to facilitate memory debugging, dynamic taint propagation and comprehensive cache miss classification are explored. All of our techniques have two common goals namely low-cost and efficiency. When possible, we incorporate programmability into hardware. This amortizes the cost of hardware by making it usable for multiple purposes. Our contributions define a new direction that renews architects' commitment to build hardware that are more programmer-friendly and help software developers achieve software correctness and performance with ease.