Research On Etching Process And Integration Of Tunneling Field Effect Transistor

With the development of the semiconductor integrated circuit industry,the scale of integrated circuits is increasing.In order to continuously improve the device performance,the feature size of the device must be gradually reduced.In the meantime,the power consumption density of the chip,however,is also gradually increasing.The total power consumption of the chip is composed of static power consumption and dynamic power consumption which are both related to the power supply voltage.The Metal-Oxide-Semiconductor Field-Effect Transistor?MOSFET?,has a theoretical limit of the subthreshold slope?SS?not less than 60mV/dec at room temperature,due to its own thermal emission mechanism.Therefore,for the MOSFET,it is difficult to reduce the power consumption of the chip by reducing the power supply voltage while ensuring sufficient driving capacity.The Tunnel Field-Effect Transistor?TFET?,however,can have a subthreshold slope of less than 60mV/dec at room temperature,due to the band-to-band tunneling mechanism.And the TFET has a very low off-state current(I_OFF)and perfect compatibility with CMOS process.Therefore,the TFETs are considered to be one of the most promising devices to replace MOSFETs in low-power applications.However,the tunnel field-effect transistors?TFET?is a gated P-I-N structure operated by band-to-band tunneling mechanism.Since the off-state leakage current of TFET is the reverse-biased P-I-N junction current,compared with the MOSFET,the TFET has a much lower off-state current,which leads to much lower static power.For the P-I-N structure of TFET on bulk substrate,the traditional twin-well processes for CMOS will increase the source-to-drain direct tunneling current.The leakage current,which may be much larger than the device off-state current,will in turn deteriorate the off-state current(I_OFF)and static power,and may even make a simple inverter consisting of two TFET devices cannot operate properly.As the integration of the circuit improves,the leakage path will become more and more complex,and its impact on the circuit will become more and more serious.Therefore,an effective leakage isolation solution for TFET integration is indispensable.Meanwhile,the metal gate etching is a very important step in the device fabrication.The TiN,one of the most general material of the metal gate,is difficult to be etched.The metal gate etching process of TFET is also urgent to be developed.We need carefully consider the etching rate,gradual etch profile,selection ratio while applying the TiN etching.To solve the above problems related to TFET in circuit integration and production,this article includes the following two parts:1)Research on the substrate leakage when TFET is applied in circuit;2)Study on the problem of gradual etch profile of TFET metal gate?TiN?during etching.When TFET is applied in a large-scale circuit,the substrate connection will lead to the problem of leakage,which will affect the TFET's advantages of low off-state current and low static power consumption.If the leakage current is too large,the logic circuit composed of TFETs may not work properly.Therefore,the problem of substrate leakage is worthy of attention.In order to solve this problem,we did a lot of simulation and data analysis for the two leakage isolation schemes of N^-WELL-PSUB and N^-WELL-PWELL which are based on the previous isolation scheme given in our group.It is concluded that the leakage isolation scheme of N^-WELL-PWELL can save more than twice the area compared with that of N^-WELL-PSUB when the isolation is effective.According to the simulation results,we carried out the tape-out experiment under the effective isolation scheme conditions obtained from the simulation.Then we tested the chip from the tape-out experiment with Agilent's 1500 probe table.The data obtained from the test was compared with the data obtained from the previous simulation,and the effectiveness of the isolation scheme was finally verified.For the problem of low etching steepness of metal gate?TiN?when producing TFET devices,we conducted three single experiments,namely 1)TiN etching experiment of photoresist,2)SiO₂ etching experiment of photoresist,3)TiN etching experiment with SiO₂ as hard mask.Finally the efficient etching conditions of TiN are obtained,which greatly improve the etching steepness of the metal gate TiN close to 85 degrees.The research on the above two aspects laid a good foundation for the application of TFETs on large circuits with low power consumption.