Highly-Parallel Hardware Implementation Of Bilinear Pairing Algorithm

Bilinear pairing over elliptic curves is the key technology to construct identity based encryption schemes.The calculation of bilinear pairing involves complex data structures and mathematical operations,so it would be time-consuming in practice.And this has become an important factor limiting its rapid promotion.To design a specialized hardware accelerator is an effective way to improve the performance of pairing calculation.In this thesis,we present a highly-parallel hardware design for optimal ate pairing over Barreto-Naehrig curves.The parallelism of the architecture is reflected at different levels,including operations in the prime field and the quadratic extension field as well as the operations based on the quadratic extension field.Especially the proposed architecture of dual quadratic extension field units at the top level makes the pairing computation more efficient.Finally,a system on chip(SoC)that contains Microblaze CPU,AXI-Lite bus and the pairing computation unit is implemented.The design is verified on a Virtex-7 FPGA device with the parameters of pairing chosen according to the Identity-Based Cryptographic Algorithms SM9 enacted by China.The results show that our design computes the optimal ate pairing of 128-bit security within 394,806 cycles,which is about 3.49 ms under the working frequency of 113 MHz,and consumes about 28 k Slices and 128 DSPs.Compared with related works,our design has some advantages in performance.Besides,the security against physical attacks of the system is also analyzed.It shows that the parallel hardware design can increase the speed as well as make the system more capable of resisting side channel attacks.