Design Of A SOI CMOS 0.1~6GHz Single-pole-double-throw Switch

The single-pole-double-throw(SPDT)RF switch is one of the most important components of the wireless communication system.It is usually located at the front end of the RF transceiver.It selectively connects the transmitter and receiver to the antenna,so that the transceiver branch can work at different frequencies.The range and the high-power signal of the receiving branch and the transmitting branch interfere with each other.With the rapid development of 3G,4G and even 5G,the high-linearity and low-interruption RF switch has become a research hotspot.This paper designs a single-pole-double-throw RF switch based on 0.28?m SOI CMOS process,with an operating frequency range of 0.1~6GHz.In order to design an excellent RF switch,this paper simulates and analyzes the capacitance and resistance characteristics of the transistor used in the RF switch in the on and off states.The RF switch is composed of a control unit module and a switch core circuit module.The control unit module is composed of a fully differential ring oscillator,a negative charge pump and a tri-state logic schematic,and the switch core circuit module is composed of a series-parallel structure switch link.In order to improve the power processing capability,the switch core series-parallel link adopts a stacked-FET structure.In order to improve the linearity and isolation,this paper introduces a control unit circuit structure that can generate a stable negative voltage,which reduces the transistor turn-off capacitance without affecting the insertion loss,thereby reducing the leakage of RF signal at the turn-off branch.The on-off state of the RF switching transistor is determined by another stable bias control generated by the control unit module.At 2.5V supply voltage,the post-simulation results in the Cadence Spectre environment show that the insertion loss is less than 0.9dB at 1GHz,the isolation is greater than 35dB,the input 1dB compression point is greater than 30dBm,and the switch-on and switch-off switching times are less than 1?s.The overall area of the layout of the RF switch with a negative voltage control unit structure is approximately 1 mm~2.The performance of the high linearity SPDT RF switch based on 0.28?m SOI CMOS technology designed by this subject meets the design specifications.After the chip is verified,it can be applied to the transmitting front end of the wireless communication system.