Research On EMMC Controller And Reliability Of NVDIMM Solid-state Disk

Twenty-first Century is the era of big data,with the rapid growth of data,the computer system is facing increasing performance challenges.In recent years,the processor and memory technology continues to progress,provides hardware support for processing massive data,and an external storage medium,such as the traditional disk,the relatively slow development,gradually unable to meet the modern application of the external storage performance requirements.Therefore,flash solid-state disk has been widely recognized and applied as an external storage medium because of its high performance,large capacity and high cost performance.But at the present stage after flash solid state flash controller still exist deficiencies in terms of performance and reliability,in terms of performance,flash memory solid state disk generally use SATA or PCIE interface,the processor must access the SSD through the external memory bus,long access path increase the access delay.In recent years,SNIA NVDIMM standard,through the use of the memory interface directly to the solid state disk inserted in the memory slot DIMM,SSD processor access by the memory bus,shorten the processor access path,reduce access delay,provides a method for flash memory solid state disk design of higher performance NVDIMM standard in this paper:(1)NVDIMM-P standard protocol design based on flash memory SSD,solid state disk using DDR3 memory interface,flash memory disk array using eMMC flash memory chip,and use the DRAM as a cache,storage hot data constitutes two hybrid storage architecture and eMMC flash array,to further improve the performance of solid state disk,use hardware and software co design way design of solid state disk controller,interface signal analysis,disk cache scheduling and flash memory access operations.(2)based on eMMC5.1 interface protocol,in-depth analysis of the eMMC flash chip working mode and bus operation,and according to the performance requirements of the overall design of flash memory solid state disk array,the design of high speed eMMC read and write controller,analyze and control the chip interface signal,realize the communication between the controller and the eMMC flash chip of HS400 mode,and correct eMMC flash memory chip initialization,read data and write data operation is verified by board level test.In terms of reliability research of flash scrubbing strategy,read-write controller free at eMMC,to detect the data of eMMC flash memory chip,detecting and correcting for bit error caused by long-term data retention,reduce uncorrectable errors.According to the characteristics of flash media,the traditional scrubbing technology is optimized,and the optimization effect is tested by constructing simulator.