Single Event Multiple Transient Effect In Nanometer CMOS Integrated Circuits

With the improvement of national comprehensive strength,space technology has developed rapidly,the performance of the spacecraft is getting higher and higher,so that large size semiconductor process can't meet the high performance requirements of the spacecraft,and more and more spacecraft is using deep nanometer technology integrated circuits.However,with the technology scaling down,charge sharing between devices becomes more serious,single event multiple transient(SEMT)has been ubiquitous in the advanced integrated circuits.Previous research has shown that the proportion of SEMT in all single events is about 20% in 65 nm twin well process,and is about 42% in 65 nm triple well process.Therefore,the study of SEMT in deep nanometer process is very urgent.In this article,we focus on SEMT in nanometer process.We conduct the research from three aspects: 1)the temperature and supply voltage dependence of SEMT in seamless guard band layout with 40 nm bulk process,2)analysis of SEMT in 28 nm process,and 3)design and verification of SEMT test chip in 28 nm process.The main results are as follows:(1)By TCAD simulation,we completely research the temperature and supply voltage dependence of SEMT in 40 nm bulk CMOS technology using seamless guard band(SGB).Meanwhile,we study the temperature and supply voltage dependence of SEMT in ordinary(Ord)layout and guard band(GB)layout,so that we can compare the temperature and supply voltage dependence of SEMT among these three layouts.Simulation results indicate that SGB layout has stronger ability of mitigating charge sharing compared with GB and Ord layouts with temperature increasing,and the SET pulse width in SGB layout shows the weakest temperature dependence.With supply voltage increasing,the SEDT production probability in GB layout is increased,but there is only SEST generated in SGB layout.Therefore,SGB layout has stronger ability of mitigating charge sharing compared with GB layout with supply voltage increasing.SGB technique is practical for the hardening of spaceborne integrated circuits.(2)We analyze the SEMT in 28 nm process.We design a test structure of SEMT in 28 nm process,which can effectively mitigate “propagation-induced pulse broadening”(PIPB)effect of SET and “pulse quenching”(PQ)effect of SEMT on the same path.The local structure of the test structure of SEMT is built into TCAD model,by which the characteristic of SEMT in 28 nm process is simulated.The simulation results indicate that single event can impact eight transistors at most in 28 nm process with FILLTIE well contact.We modify the FILLTIE well contact to the stripped well contact.The simulation results indicate that single event can impact four transistors at most in 28 nm process with stripped well contact.Therefore,charge sharing is extremely common in 28 nm process,and SEMT becomes a common modality of SET.(3)Based on a commercial 28 nm process,we design a SEMT measurement chip.This chip consists of the target circuit,the measurement circuit,debug circuit and ring oscillator circuit.The measurement accuracy of the measurement circuit is 6.92 ps,and the maximum detectable pulse width is about 1 ns.We conduct the post-simulation verification with parasitic parameters for the SEMT measurement chip.The error in the simulation results is acceptable,and the SEMT measurement chip can realize the measurement of SEMT.Besides,we introduce the ground radiation test system and experimental scheme of 28 nm SEMT.We focus on SEMT in nanometer process in this article,and make some progress in mechanism of charge sharing,TCAD modeling and chip design.Some meaningful conclusions are obtained in the research.Forecasting the research in the future,we think it is meaningful to do some research in the following aspects: 1)the influence of low LET ion with angle incidence to seamless guard band(SGB),2)the radiation test of 28 nm SEMT test chip,3)the frequency dependence of SEMT.