High Speed Divider Design By 28nm CMOS Technology

With the evolution of the 5G communication technology,millimeter wave communication has become a new research hotspot.As an essential part of millimeter wave communication,high-frequency phase-locked loop(PLL)has attracted more and more attentions.The high speed frequency divider studied in this paper is an important module in PLL,which determines the performance of PLL and transceiver.In this paper,we have selected the ILFD as the basic structure.And we presented two high speed Injection-Locked Frequency dividers,one is a divide-by-2 divider,and the other is a divide-by-3 divider.After a thorough investigation,we have found that the Injection-Locked Frequency divider has the defect of narrow locking range.By combining three methods,dual-end injection for transconductance enhancement,substrate bias technology,and harmonic enhancement technology,a wide locking range and low power consumption high speed divide-by-2 divider can be realized.However,due to the difference between divide-by-2 divider and divide-by-3 divider,the harmonic elimination method has been adopted,and the locking range of the divide-by-3 divider has also been improved.Based on the UMC 28 nm CMOS process,this paper has completed the design,layout,and post-simulation of the above mentioned high speed injection locking divide-by-2/3 frequency divider.The performance is as follows: the divide-by-2 divider can achieve a locking range from 31.1 to40.1GHz with only 4.72 m W power consumption,which has certain advantages in the highest locking frequency and locking range compared to other divide-by-2 dividers in the literature.The divide-by-3 divider canwork in the frequency range of 32-36.4 GHz,with a locking percentage of12.1% at the power consumption of only 5.37 m W.