Design Of Tunable True-time Delay Circuit Based On Digital Control

The true-time delay?TTD?circuit has been widely applied in the radio communication and the optical-fiber data transmission systems because of its broadband,delay and other excellent characteristics.For example,the phased array radar system with a TTD phase shifter instead of a traditional phase shifter can eliminate the beam squint and reduce the bad influence of non-linear factors such as transit time and aperture effect,while the signal-to-noise ratio?SNR?and the communication capacity are improved.A TTD circuit is used in the feed-forward equalizer to compensate for signal distortion caused by differential mode delay?DMD?.The TTD circuits are mainly divided into optical TTD circuits,digital TTD circuits and analog TTD circuits.The analog TTD circuits have attracted much attention due to wide bandwidth,easy integration and good group delay performance.With the advent of 5G era,it is of great significance to study analog TTD circuits.On the basis of studying the theory of delay cells and analog TTD circuits,a new analog TTD circuit is designed with 0.18?m standard CMOS technology,which is based on the design ideas of"combining passive delay circuit and active delay circuit to improve the product of group delay and bandwidth"and"combining coarse-tuning and fine-tuning to increase the group delay range".The TTD circuit has the characteristics of digital control,tunable group delay and large group delay range.The TTD circuit is divided into four modules.The active coarse-tuning delay module is composed of eight coarse-tuning delay cells and seven single-pole-double-through?SPDT?switches.The sub-unit of a coarse-tuning delay cell adopts active inductor parallel peaking structure to expand bandwidth.SPDT switches,which are connected with the 3-bit digital control module and the coarse-tuning delay module,achieve the purpose of digital control.The static CMOS logic gate circuits generate a 3-bit digital control module,which reduces design difficulty.The four-stage?-LC delay circuit serves as the passive fine-delay module,which can minimize group delay accuracy and meet the requirement of large bandwidth.The inter-stage matching module which consists of coarse-tuning delay units and a NMOS source follower,can not only match the coarse-tuning delay module and the fine-tuning delay module,but also compensate for gain loss.The post simulation results of coarse-tuning and fine-tuning delay modules show that the coarse-tuning delay module gets a coarse-tuning step of about 24ps with the process-corner jitter of 2%¹1.9%over a frequency span of 3GHz⁴GHz.Moreover,it generates an excellent linearity of relative group delay versus3-bit digital control.The fine-tuning delay module offers a continuous tuning range from 0 to 30ps.The process-corner jitter of the maximum fine-tuning relative group delay is 2.2%⁵.8%.In addition,the transient simulations of coarse-tuning and fine-tuning group delay are almost the same as those of SP simulations.The continuity condition of group delay is satisfied at all process corners,including TT?SS and FF.The post simulation results at TT process corner of the tunable TTD circuit based on digital control demonstrate that the working frequency band is from 3GHz to 4GHz,and the S₃S₂S₁ of 3-bit digital control makes the coarse-tuning delay module achieve seven discrete relative group delays,which are 24.50ps,49.20ps,74.30ps,99.21ps,124.20ps,149.00ps and 173.60ps respectively.Thus the coarse-tuning step is about 24.50ps.Moreover,the fine-tuning delay module controlled by Vc gets a continuous fine-tuning range from 0 to 29.37ps.Under the co-control of S₃S₂S₁ and Vc,the TTD circuit has a continuous-tuning relative group delay of 0²03ps with a max delay variation of 7.74%and a max gain variation of±3.83dB.The calculated value of the product of group delay and bandwidth and the ratio of group delay to area are203ps·GHz and 441ps/mm² respectively.Besides,this TTD circuit achieves good input impedance matching with S11 of less than-15dB,mediocre output impedance matching with S22 of less than-6.6dB as well as superior isolation performance.Furthermore,the noise figure is maintained at about 33dB.Lastly,the DC power consumption is about 77mW and the chip area is 0.46mm2.All performances of this tunable TTD circuit based on digital control meet design expectations.