Bandwidth And Locality Aware Task-Stealing For Manycore Architectures With Bandwidth-Asymmetric Memory

Parallel computers now start to adopt Bandwidth-Asymmetric Memory architecture that consists of traditional DRAM memory and new High Bandwidth Memory(HBM)for high memory bandwidth,which is one kind of Hybrid Memory.However,existing task schedulers are designed for the compute-intensive applications and focus on conventional single memory architecture,they suffer from two main problems which are low bandwidth usage and poor data locality in the new memory architectures.To solve the two problems,we propose BATS,a task scheduling system that consists of an HM-aware data allocator,a bandwidth-aware traffic balancer,and a hierarchical task-stealing scheduler.Leveraging compile-time code transformation and run-time data distribution,the data allocator enables HBM usage automatically without user interference.According to the data access hotness,the traffic balancer migrates data to balance memory traffic across the memory nodes proportional to their bandwidths.The hierarchical scheduler improves the data locality at runtime without priori program knowledge.Experiments on an Intel Knights Landing server that adopt the HM architecture show that BATS reduces the execution time of memory-bound programs up to 83.5% compared with traditional task-stealing schedulers.