High-resolution Noise Shaping SAR ADC

In modern communication systems,a large number of high-precision analog-to-digital converters are in demand.In order to increase the integration,the area and power consumption are required to be as small as possible.The successive approximation register analog-to-digital converters(SAR ADC)is low power consumption and small area,but the noise of the comparator limits its resolution.The delta-sigma analog-to-digital converter is the most popular structure for achieving high SNDR.However,it is high power consumption and large area because of a great deal of operational amplifiers used.The noise shaping successive approximation register(NS SAR)ADC combines the advantages of low power consumption,small area of the SAR ADC,and high resolution of the delta-sigma ADC,which attracts increasing attention in the field of high-precision analog-to-digital converters.The NS SAR ADC is implemented for the modern communication system with SNDR>75dB,bandwidth of 12.5MHz.The ADC is composed of a 10-bit SAR ADC and residue voltage process.In order to improve the bandwidth,two-channel interleaving technique is applied.Although there are offset errors,gain errors and time errors between channels when interleaving,the harmonics introduced by these errors are outside of the bandwidth due to oversampling,which adds little overhead.In high-precision ADCs,the value of capacitor array is so large that the build-up of voltage is slow and the drive capability of the reference voltage buffer is supposed to be high enough.To solve these problems,a 4-bit auxiliary ADC is used to obtain the result of the four MSB bits,and works at twice the single-channel sampling frequency to be shared by the two channels.A redundant bit is added to cover the offset between the auxiliary ADC and the main channel,which also reduces the setup requirements of the capacitor array's voltage.In order to obtain more stable noise shaping performance,the dynamic operational amplifier is replaced by a high linearity conventional operational amplifier at the cost of slightly higher power consumption.In addition,a second-order capacitor mismatch error shaping(MES)siwtching scheme is peoposed,which only requires an extra reference voltage.The simulation results shows the SNDR and SFDR inprove about 14dB and 20dB,respectively.The presented NS SAR ADC is implemented in TSMC 40nm CMOS process,which occupies an active area of 0.188)8)~2.Post-simulation results show that the ADC exhibits 79.3dB SNDR and 6.52mW power consumption under a 1.1V supply voltage when input signal frequency and amplitude are 4.69MHz and 0.8V at 200MS/s sampling frequency,which leads to FoM 172.3dB.Consequently,the results meet the high-resolution design requirement.