Low-Power Cache Design Based On Non-Volatile Memory

Memory wall(memory and CPU speed difference)can be alleviated by increasing the capacity of the last level cache(LLC).However,due to the large area and static power consumption,the capacity growth of traditional SRAM LLC has appeared a bottleneck.Nowadays,non-volatile memories,such as electronic spin-transfer RAM and resistive memories,have the characteristics of low static power consumption,high storage density,and high performance.It is very promising to replace current SRAM as on-chip cache.However,the write operation of this type of non-volatile memory often consumes a lot of energy and has a high latency.Direct replacement of the SRAM cache will cause the additional energy consumption of the write operation to offset the advantages of non-volatile memory.Before real industrial applications of such non-volatile caches need to be optimized for such memory write operations.By analyzing the reuse information of the last level cache by various applications,a dynamic bypass strategy(Re BP for short)based on cache block reuse information is proposed to optimize the non-volatile memory as the last level cache zone High energy consumption.This scheme analyzes the reuse information of the cache block to dynamically select whether the cache block bypasses the non-volatile memory.There are two ways to fill NVM LLC,one is from L2 write back,and the other is from LLC missing fill.Re BP performs bypass analysis from these two aspects,in which L2 write back bypass strategy adds high Cache monitoring module(CM),which has two modes:interval query and real-time query.In different modes,the CM module can learn the status information of multiple L2 caches to dynamically select the bypass path.The bypass strategy we proposed can knock out most of the write operations.Traditional bypass operations will reduce the LLC hit rate and cause performance degradation.But our strategy skillfully adjusts the bypass,overcomes the hit rate loss,and improves performance.LLC missing padding uses the reuse information of the cache block and the prediction information of the prediction table to jointly determine the bypass strategy of the cache block.The design of the scheme will improve the performance of the overall cache.Through experimental analysis,compared with the STTRAM LLC benchmark,Re BP can reduce the execution time of all SPLASH-2 applications by 6.6% on average in a4-core system,while reducing the energy consumption of NVM LLC by 22.5% on average.In our experiments,we evaluated other existing architectural designs.Oursolution has a significant improvement in performance and energy consumption,so that non-volatile memory becomes the last level of cache technology and becomes the future of high-performance computing.Attractive alternative.