Research On Software And Hardware Collaborative Verification Of Reconfigurable Multi-core System

With the advancement of integrated circuit industrial design technology and semiconductor manufacturing technology,the computer's processor has transitioned from the original single-core single-thread to multi-core multi-thread.At the same time,in order to meet the specific scene needs such as machine learning training and image processing,integrated dedicated IP Reconfigurable multi-core systems are starting to appear.The reconfigurable multi-core system is an extension of the configurability of multi-core processors.Its extremely high hardware design and functional complexity increase the difficulty of system verification and cost investment.In response to such problems,how to obtain an efficient and universal solution to cover the entire system verification needs has become a hotspot in academic circles.Based on the idea of software control and hardware collaborative acceleration,this paper designs and implements a multi-threaded simulation acceleration platform for software and hardware collaboration of reconfigurable multi-core systems.On the premise of satisfying verification requirements,a software system framework matching the hardware side is constructed.The main contributions are as follows:First,the platform adopts a layered design and task execution drive strategy,and integrates the multi-precision model of the hardware target system as the control layer,which is responsible for task configuration delivery,source data generation,output verification,and error analysis.The downstream hardware prototype serves as a reconfigurable hardware acceleration node for computational simulation tasks.The subtasks are concurrently executed according to the configuration rules of the simulator control layer,and its output is returned to the upstream simulator through the PCIe interface.The needle module performs real-time monitoring and external feedback on the working status of the hardware prototype.Second,the paper combines the advantages of target hardware system task concurrency,the software side adapts the hardware side PCIe interface driver,and the system simulator is designed with a multi-threaded programming interface to support concurrent task programming.The data calculation undertaken by the software simulator during the whole system simulation will be concurrently sent to the multi-core system for accelerated execution.In order to simplify the management of the working thread of the target system,a line-based task monitoring strategy is adopted in the simulator.Next,in order to speed up the task pre-processing speed,the design of the compiler optimization layer is based on the system mixed precision simulator.According to the hardware instruction set specification of the system's secondary programming architecture,the dynamic task translation and real-time compilation techniques are used to perform the system task program.Compile and execute optimization.The platform component design re-normalizes the routing node and computing cluster communication interface with interface encapsulation according to the details of the on-chip network communication of the target system and the characteristics of the computing cluster architecture,so that the system components present unified programming specifications to the outside,which improves scalability and transplant performance.Finally,this paper conducts joint debugging of software and hardware on the design platform to evaluate the simulation speed and accuracy,design defect localization capability and system task concurrent performance in various algorithm calculation scenarios.