Research On Timing/Counter IP Core For 8/16 Bit Microprocessor

A large number of timers / counters are used in large scale timing / counting control systems or other 8/16 bit microprocessor applications.Therefore,it is a trend to expand the number and range of timers / counters to meet the needs of the industry.By analyzing the function of timer / counter and using FPGA characteristics,the architecture of timer / counter IP core is designed for dynamic parallel execution.The static reconfigurable timing / counter IP core is designed,which can be used to change the number and range of the internal timer or counter according to the specific engineering application requirements,so as to realize the flexible configuration of the FPGA resources on the IP.The following achievements have been obtained in the research:?1?The design of the interface circuit of the 8/16-bit microprocessor and the IP core,the design of the reading and writing time sequence,and the instruction format of the microprocessor controlling the timer and counter are completed.?2?The design of timer is completed.According to the design idea of parallel processing between modules,the timer is divided into functional modules,in which the timing control module is implemented in a pseudo sequential operation,and all the timers are operated in 1us to realize the timing or output PWM pulse modulation signal.The parallel processing of modules enables each module to process tasks in parallel,without the influence of other modules.Timing accuracy is 1us,timing range 0.1ms?2³²*100ms.?3?The design of counter is completed.According to the design idea of parallel processing between modules,the counter is divided into function module,in which the counting processing control module adopts the method of cyclic scanning to detect the external counting signal source.The external signal is judged according to the FSM to determine whether each counter is executed,whether the up / down count and other operations to achieve the external signal count,frequency measurement or measurement cycle,etc.The maximum count frequency is 684.9KHz.?4?The system structure design of static reconfigurable timer / counter is completed.The bit width of timing / counting and the number of the timer / counter are as variables,when the demand is determined,set the number of the timer / counter and the bit width of timing / counting,compiled the program,integrated layout and wiring,downloaded to the board level,to achieve the timer / counter number and scope of the reconstruction,the design does not change the internal logic of the IP core and instruction format.The design method of local dynamic reconfiguration is proposed.?5?The correctness of the timing / counter function is verified by the simulation test and the board level debugging,and the designed timing / counter is encapsulated into the IP core.The simulation tests verify the timing error is not greater than 1us;the maximum count frequency value is 684.9KHz.Reconfigurable timer timing error is not greater than 1ms;N counters used at the same time the maximum count frequency is 1/(N*14*2*T_??)(T_?? is the system clock cycle).