Design Of The 5Gbps 10:1 Parallel-to-Serial Conversion Chip Based On 130nm CMOS

Serial transmission is widely used because of its stability and reliability under high-speed data transmission and cost savings.However,the internal processing of the system still adopts parallel mode,so that the parallel-to-serial conversion SerDes(Serializer/Deserializer)chip plays a very important role in the high-speed digital communication system.With the continuous improvement of transmission rate and the continuous development of interface circuits,the performance requirements of SerDes chips in serial communication systems are becoming higher and higher,such as high speed,low power consumption,low voltage,etc.Specific to the design of the SerDes chip,as the rate increases,it also brings challenges in terms of bandwidth,timing margin,and index assurance under multiple process angles.This article designs a 5Gbps low power 10:1 serializer chip based on the domestic 130nm CMOS.The chip can receive ten channels of parallel 500Mbps datas and output one channel of serial 5Gbps data,which is mainly received by clock It is made up of modules such as device,ten parallel data receiving,PRBS,5:1,2:1,serial data sending.Among them,the 5:1 module uses a multi-phase structure to convert 5 channels of parallel 500Mbps data into 1 channel of serial 2.5Gbps data;the 2:1 module uses a tree structure to convert 2 channels of 2.5Gbps data output by the 5:1 modules into 1 channel 5Gbps data.The overall area of the chip is 1.5mm*1.2mm,and the power consumption is 34.8mW.The specific research content and innovation of this article are mainly reflected in the following two aspects:1.A customized multi-level latch structure is used in the 2:1 module to ensure the timing margin of data and clock.The sampling node of the output data of the 2:1 module is the node with the highest frequency,which has strict requirements on the timing.Therefore,the front stage of the 2:1 module adopts a two-way customized multi-level latch structure,and the latter stage adopts a tree structure.The first sequence consists of 2 latches,and the second sequence consists of 3 latches.The phase of the data passing through the two sequences is determined by the clock edge,and the tree structure uses clock strobe data.The 2:1 module with this two-stage structure ensures that the timing is only related to the clock,and no buffer is required for phase adjustment,thereby avoiding phase deviation at different process angles and temperatures,and achieving sufficient timing margin.2.APRBS source module is added to the chip,and the 10-channel parallel input data provided by the module is used to realize the self-check function of the chip.The customized multiplexing structure composed of D flip-flop and XOR gate is used as the core circuit and the PRBS7 sequence is cyclically output in a ten-way parallel mode.The serial data after parallel-to-serial conversion is the PRBS7 sequence,thereby realizing chip self-checking.The chip has been designed and taped out.On this basis,a special test board based on the Xilinx KC705 development board has been designed to implement the chip self-test function test.The test results show that PRBS,clock reception,frequency division,5:1,High-speed 2:1 and other core modules work normally and meet the timing requirements.The measured power consumption is 34.8mW.