The FPGA Design For Bridge Target Detection In High Resolution SAR Images

With the rapid development of Synthetic Aperture Radar(SAR)imaging technology,high-resolution SAR image processing is becoming more and more widely used in military and other fields.The high-resolution SAR image data obtained through imaging is also more and more processed.Image data often takes a long time and cannot meet the requirements of real-time and accuracy of high-resolution SAR image processing,especially in the rapidly changing military field of the battlefield environment.Heterogeneous computing is a high-speed means of processing massive amounts of data at present.CPU+GPU is the most common heterogeneous computing architecture at present.GPU has strong computing power,which makes it uniquely advantageous in the field of parallel computing.However,with the continuous expansion of GPU clusters,power consumption and heat dissipation problems have gradually emerged,which has become an important constraint factor for GPU to perform parallel computing.The emergence of OpenCL heterogeneous computing standards allows developers to develop FPGA in C language without having to learn traditional hardware description languages,making FPGA a big step in high-performance computing,in order to efficiently handle high resolution.SAR images are available.At present,there are many bridge detection algorithms for high-resolution SAR images.The SAR image bridge detection algorithm based on corrosion and expansion operation,which is relatively simple and parallel,is the research object.It is implemented in parallel on CPU+FPGA heterogeneous platform.The execution efficiency of the algorithm is improved.Finally,the parallel execution of the algorithm is optimized and accelerated by various means,and the efficiency of the bridge target detection is further improved.The main work of the thesis is as follows:(1)In this paper,the high-resolution SAR image bridge target detection algorithm based on corrosion and expansion operation is first implemented on the CPU platform.Secondly,using the CPU+FPGA architecture,the parallel target acceleration of the bridge target detection algorithm already implemented on the CPU side is carried out.The OpenCL kernel program is implemented in four parts in parallel to realize the algorithm function:the first step is to realize the Lee filter in the SAR image preprocessing.The function is parallelized;the second step is to realize the threshold segmentation and the median filter function parallelization in the river region segmentation;the third step is to realize thecorrosion expansion operation in the bridge detection and the parallelization of the binary image XOR operation function;The step is to realize the parallelization of the segmentation of the bridge area.Compared with the implementation of the bridge target detection algorithm based on the CPU platform,the preliminary parallelization based on the FPGA heterogeneous computing platform greatly shortens the detection time of the SAR image bridge target,improves the program running efficiency,and has the detection effect equivalent to the CPU platform.(2)Because FPGA configuration state has a great impact on OpenCL execution,this paper is based on the preliminary parallelism of FPGA heterogeneous computing platform for bridge target detection algorithm,from global memory optimization access,loop expansion,setting appropriate working group size and vectorization.In terms of aspect,after a lot of experiments,further optimization and acceleration schemes of parallel programs were determined.Finally,the bridge target detection effect based on FPGA heterogeneous computing platform optimization is compared with the detection effect based on FPGA parallel computing.The feasibility of optimizing the acceleration scheme is verified,and the implementation speed of the algorithm is further improved.