Parallel Calculation Of Speed-Up SAR-SIFT Algorithm Based On Multi-core DSP

SAR is an important technique for obtaining remote sensing images,and the result is a grayscale image of the beam coverage area.With the increasing quality of SAR images,the application of SAR images has been widely concerned by scholars all over the world.In the navigation field,the SAR image matching technology is used for carrier positioning,which plays a role in correcting INS and GPS errors,and can support high-precision positioning for a long time that has important application value.Compared with the early gray-based matching algorithm,the feature-based matching algorithm has obvious advantages in affine invariance and scale invariance of images.It is more robust for SAR image with speckle noise,high dynamics and geometric deformation.However,in general,the feature-based matching algorithm has a complicated computational structure and a large amount of computation,which is not easy to implement.The purpose of this paper is to implement algorithm based on feature in real time.A combination method of "scale space dimension reduction + step-by-step extreme value detection + average weight small neighborhood" is proposed for feature-based SAR-SIFT matching.The algorithm accelerates,which greatly improves the computational efficiency of the SAR-SIFT algorithm while ensuring the effect of the algorithm.And the implementation of the engineering implementation platform and the multi-core parallel computing of the SAR-SIFT acceleration algorithm are also implemented.The main work of this thesis is as follows:1.Research on SAR-SIFT algorithm acceleration method.The time-effect of feature-based SAR-SIFT matching algorithm depends largely on the number of feature points and the dimension of the feature vector.This paper combines the "scale space dimension reduction + step-by-step extreme value detection + average weight small neighborhood" combination.Specifically,the calculation amount is reduced by reducing the space with less scale space,and the spatial neighborhood feature detection method is replaced by the faster step feature detection,and the weighted small neighborhood is replaced by the weighted large neighborhood to reduce the dimension of the feature vector.Under the premise of algorithm performance,the computational efficiency of the algorithm is improved,and the code size is reduced.2.SAR-SIFT acceleration algorithm computing platform design.In this paper,combined with the computational characteristics of SAR-SIFT acceleration algorithm and the recognition of SAR image matching in SAR imaging system,the functional design and reasonable computing resource allocation of its computing platform are carried out.In order to make full use of the computing resources of the platform,the SRIO interface and the Hyper Link interface are realized and tested separately.The key technologies of TMS320C6678 like thread communication based on SYSLINK,multi-core synchronization based on Notify or hardware semaphore,and matrix transposition based on EDMA3 are implemented.3.SAR-SIFT acceleration algorithm multi-core parallel implementation.Based on the computational analysis and module planning of SAR-SIFT acceleration algorithm,the SAR-SIFT acceleration algorithm is divided into three parts: scale space establishment,scale correlation and non-scale correlation.The feasibility analysis of multi-core parallel calculation for each part of the algorithm is proposed.The scale space is built to correspond to 8 cores for synchronous operation,the scale correlation part corresponds to the kernel layer one-to-one,and the non-scale correlation part performs 8-core synchronization operation;according to the load analysis of the data interface,the calculation module of the algorithm is rationally allocated on the limited computing resources;combining the advantages of the master-slave mode and the data stream mode,the software architecture of the function-corresponding task is proposed.This architecture can extend the function without changing the overall structure;the implementation code is compiled and optimized,tested for performance.