Research On Performance Optimization Of Configurable Parameters Based On BOOM Superscalar Processor

With the rapid development of integrated circuit process technology and the increasingly complex microprocessor design requirements,researchers must minimize the microprocessor design cycle.Due to exploding design spaces,increasing design complexity and long-running workloads,it has become increasingly difficult to perform design space exploration(DSE)of microprocessors with a short time.Researchers have used typical search optimization techniques to accelerate design space exploration,such as simulated annealing,genetic algorithms.Even though these technologies can speed up the exploration of design space to some extent,they still take a lot of time to do the DSE.The main reason is that typical search optimization techniques cannot understand how different parameters within the processor affect the performance of the processor and only treat the microprocessor as a "black box".Therefore,how to speed up the exploration of processor architecture design space becomes more and more important.The thesis proposes a method of criticality-driven simulated annealing algorithm for processor design space exploration(CDSA-DSE).Firstly,the critically driven disturbance information is used as the random disturbance of the simulated annealing algorithm,and the simulated annealing algorithm is provided with the local information of the adjacent region of the current design point.Then the pruning strategy of the superscalar design space is proposed to narrow the scope of the design space to be explored.Finally,the criticality analysis method is introduced in detail,and the model of the super-scalar processor's issue queue is added.The combination of criticality analysis and simulated annealing algorithms can effectively accelerate the DSE.In addition,the method is also applied to the superscalar processor called BOOM,and then the BOOM is optimized based on timing to improve its frequency.This paper optimizes the decode and register renaming stage of the BOOM's pipeline and the multiplication module of the fixed-point execution unit,and optimizes the TLB miss processing mechanism of the Load/Store Unit,the memory ordering failure detection mechanism of the Load/Store Unit,and cancels the characteristics of AMO instructions' blocking instructions.For the benchmarks SPEC CPU 2006,on average,CDSA-DSE achieves 2.1x speedup over the DSE based on the typical simulated annealing algorithm.Sensitivity studies by changing the starting point and design space size also show that CDSA-DSE is superior to the DSE using only simulated annealing algorithms.Based on the SMIC 40 nm process,the logic synthesis of BOOM structure before and after optimization is carried out.The simulation results show that BOOM's performance of the application is reduced by 4.46%,and its frequency is increased by 14.2% under the worst process corner.The above results show that this design meets the design specifications of BOOM processor performance optimization.