Research On The Key Techniques Of High Speed CMOS Time Domain A/D Converter

With the development of science and technology and people's increasing demand for quality of life,wireless,portable and wearable devices are increasingly appearing in daily life.As the bridge between analog signal and digital signal,analog-to-digital converter(ADC)plays an important role in the whole system.And high-speed,medium-resolution ADCs have been widely used in these wireless sensor devices.At the same time,the continuous progress of semiconductor manufacturing technology and the reduction of supply voltage make the design of analog circuits more and more challenging,while the propagation delay of CMOS transmission gate decreases.Therefore,compared with the traditional voltage-domain architecture,the time-domain ADC can benefit more from the shrinkage of process and the reduction of supply voltage,thus achieving better performance.In view of the above problems,this thesis will focus on the research and analysis of the system architecture as well as key technologies of high-speed CMOS time-domain ADC.In this thesis,the design of high-speed CMOS time-domain ADC is systematically studied,and the non-ideal factors in the system are deduced and analyzed.Taking the design of a time-domain ADC as an example,the key technologies of high-speed time-domain ADC are discussed in detail.Firstly,the linearity and accuracy of sampling are improved by optimizing and improving the traditional sampling network.The simulation results show that the signal to noise and distortion ratio and the effective number of bits can reach more than 86dB and 14bits in Nyquist band,which lays the foundation for the overall conversion accuracy of ADC.Secondly,a novel structure of voltage to time converter(VTC)with large input dynamic range and high linearity is proposed.Compared with the traditional structure,it is able to solve the contradiction between input dynamic range and conversion linearity,which can improve the linearity of VTC as well as increase the input signal swing.Then,a high linearity current source is implemented to solve the contradiction between the large input swing with low supply voltage and the high output impedance of current source.Finally,a novel two-step time to digital converter(TDC)structure is proposed,which combines coarse quantization with fine quantization and the optimal segment ratio of integer part to decimal part is determined by modeling and simulation analysis,which can effectively reduce the overall area and power consumption.The prototype was fabricated in TSMC 65nm 1P9M 1.2V standard CMOS technology,and the chip area is 130×400?m~2.The measurement results show that under the condition of1.2V supply voltage and 400MS/s sampling rate,the ADC can achieve 57.8dB spurious free dynamic range(SFDR),49.2dB signal to noise and distortion ratio(SNDR)and7.88bits effective number of bits(ENOB)when the input frequency is 12.1MHz as well as58.9dB SFDR,48.3dB SNDR and 7.73bits ENOB when the input frequency is 197MHz.The power consumption is 3.9mW,and the corresponding figure of merit(FoM)is41fJ/conv.-step.In terms of static characteristics,the DNL of the chip is within+0.4LSB and-0.4LSB,and the INL is within+1.3LSB and-0.8LSB.