Research On Power Analysis Of Criptographic Algorithm Based On FPGA

Computer and Internet technology are the foundations of today's information society.The generation,processing and dissemination of various information have become an essential part of people's lives.Nowadays,All kinds of cryptographic devices equipped with cryptographic algorithms guarantee the secure transmission of information.Therefore,their security is paid more and more attention.In recent years,side channel attacks,especially the most popular differential power analysis are gradually emerging,which have the advantages of low attack cost and high attack efficiency so that they pose a great threat to the existing cryptographic devices.At present,during the evaluation and certification process of cryptographic products,differential power analysis will always be performed.As a consequence,it has both theoretical value and practical significance to study the corresponding countermesures for bypass power analysis.FPGA has a strong flexibility and can be used as a hardware simulation platform to evaluate the security of cryptographic algorithm implementation.It is the reason why FPGA is chosen as the experimental platform in this paper.This paper mainly studies the power analysis and corresponding protection techniques of cryptographic algorithms based on FPGA.The following specific work has been carried out.1)The classifications and principles of bypass power analysis and protection techniques have been studied and grasped deeply,which lays the theoretical foundation for the experiment.2)A power collecting platform based on FPGA is constructed,which is applicable for the vast majority of cryptographic algorithms.In order to improve the analysis efficiency,various methods are proposed to improve the speed and quality of power trace collection.3)The methods and steps of power analysis are studied aiming at AES and SM4 algorithm.Corresponding countermeasures are put forward based on hiding and masking techniques.4)Some protection schemes have been realized for power analysis experiments.Their pros and cons are analysed so as to sum up the methods to improve the security of cryptographic circuit.The experimental results show that the number of power traces needed to perform a successful analysis of mixing hiding and masking implementation of AES circuit has been increased to more than 500000 compared to the unprotected AES circuit,which just needs 7000 traces.Meanwhile,it takes a successful chosen plaintext attack to ultimate protection implementation of SM4 50 times more number of power trace than the naked one.This proves the effectiveness of the countermeasures proposed in this paper.In order to improve the design ability of secure circuit,this paper not only gives the comparison of each protection implementation,but also discusses other factors that affect the circuit security.In addition,this paper finally makes a study on the difference of power analysis between FPGA implementations and real chips.