Design Of Ultra High Definition Video Encoder IP

This paper presents an ASIC based ultra-high definition video encoder IP core that supports the HEVC video codec protocol,with a maximum coding speed of 30 frames per second for 4096x2304 resolution images.In order to satisfy both high compress quality and fast process speed,the IP has designed lots of innovative algorithm modules such as motion estimation,SAO,data access/storage and so on.The motion estimation has the architecture of three grade precision.Each grade has its dedicated search strategy and cost function,especially for the first grade which has the largest search range,we designed a new strategy which combined two level block search strategy with the motion information of surrounding blocks.It solves the problem of that big block search is not accurate on motion boundaries while small block search has poor motion consistency.Furthermore,we extract the encoding block feature,adaptive adjust the weight of block matching portion and motion consistency portion in the cost function.This makes the result of motion estimation more accurate and consistent.For the SAO encoding module,we propose a new pre-judgment algorithm which uses the spatial distribution feature of current encoding block to reduce the amount of calculation.As for data access and storage,we have designed a dedicated CACHE with lossless data compression engine,based on the encoding data access feature.It significantly reduces the bandwidth of external data access.After the large number of algorithm optimizations,the encoding performance is obviously improved,especially in low bit rate scenario,performance advantage could reach 4dB.