The Design Of Broadband Pluse Signal Conditioning Circuit

Timing data generators are widely used in the fields of data domain and communication system testing.As an important test instrument in the field of modern digital generation technology,the timing data generator can generate programmable sequence pulse signals with parameters such as frequency,amplitude,level,slew rate and cross point of the eye.This paper combines the scientific research topics of “Timing Data Generator”,the multimodule,multifunction broadband pulse signal conditioning technology and circuit design.Aiming at the higher requirements of signal data rate,level and amplitude,new functions of the slew rate and cross point of the eye control and source impedance transformation(50 ?/23 ?),different schemes are designed by using linear conditioning technology.In addition,the results of various simulations and corresponding circuit designs are presented.Finally,the nonlinear conditioning technology is designed and completed under the requirement of the subject index.The multimodule pulse signal conditioning circuit realizes the broadband signal conditioning function.The main research contents of this paper include:(1)The time and frequency domain characteristics of broadband pulse signals and the technical requirements corresponding to the technical difficulties of conditioning are analyzed.In this paper,both linear and nonlinear conditioning technologies are analyzed,and different signal conditioning modules based on nonlinear conditioning technology are designed.(2)For module 1,with the highest data rate of 700 Mbps,and module 2 and module 4,with the highest data rate of 1.1 Gbps,a self-developed differential variable gain amplification scheme is adopted to fulfill the design requirements and achieve high power amplification and level offset of the broadband pulse signals.Module 1 requires that the slew rate can be controlled by using a step size of 0.01 V/ns in the range of 0.65 V/ns to 1.3 V/ns at frequencies below 50 MHz.The solution proposed,is based on the pin driver control of the signal slew rate.(3)Module 3,with the highest data rate of 3.35 Gbps,adopts a design scheme based on the pin driver,RF attenuator and bias tee.Module 3 requires the control of the cross point of the eye diagrams under the NRZ pattern,digitally reconstructs the pattern waveform and adds a time variable to precisely control the data edge in the reconstruction process,so that the cross point of the eye diagrams can be controlled by using a 2% step in the range of 30%~70%.(4)The board design and signal integrity of the high-frequency signal conditioning circuit were analyzed.The debugging methods for each module are discussed and analyzed,and the solution is given.