Research On Automatic Test Method Of FPGA Interconnect Structure

FPGA,is the abbreviation of Field Programmable Gate Array.Since twentieth Century 80 s,the development of Field Programmable Gate Array has been progressing.FPGA is a field programmable dedicated integrated circuit,Due to this characteristic,The FPGA series of devices are becoming more and more popular with circuit designers and manufacturers.The main development direction of FPGA is that the integration is getting higher and higher,the performance is becoming stronger and the internal structure is becoming more and more complex.All of this gives FPGA a sharp increase in the difficulty of testing.But as the difficulty of testing improves,FPGA designers and manufacturers also are becoming to pay more and more attention to the stability and reliability of FPGA.In short,the effectiveness of FPGA testing is directly related to the production design cycle of FPGA products and the cost of research and development.At present,most of the existing test methods are only suitable for Xilinx XCV chip,and can not effectively test Virtex-4 series FPGA.For metal interconnect wire test,most configuration is connected by man-made,which requires great time cost.This thesis is based on the current known test methods that do not meet the needs of FPGA interconnect structure testing,and the prerequisite for achieving test requirements is to reduce the number of test cases with the maximum coverage of the test cases as high as possible.So in view of the current situation that there is no method or no better way,this thesis develops an automated test method based on the internal interconnection structure of Virtex-4 series FPGA devices of Xilinx company.To achieve the goal of reducing the cost of testing for Virtex-4 series FPGA devices,the high coverage rate of metal interconnect wire resources is achieved under the premise of the minimum number of configurations.The main research contents are as follows:(1)Modeling the internal interconnect structure of Virtex series FPGA.Taking Virtex-4 series FPGA chip as the research object,modeling the basic unit of FPGA,and classifying the FPGA intermetallic lines by induction,and establishing all kinds of metal interconnect models.Then,based on the graph theory and the related knowledge of graph theory,the interconnection structure of FPGA's internal metal interconnect wire is abstracted to express and study the establishment of metal interconnect wire resource model diagram,so that the resource model diagram can be well applied to Virtex series FPGA.(2)A method for testing the X1 line resources of Virtex-4 series chips is proposed.By studying the internal SLICE structure of CLB in Virtex-4 chip,and based on the idea of deterministic fault detection,we propose a fixed line rule for generation configuration graph,and get the X1 graph resource configuration test graph with high coverage under a small number of test configurations.The test method can detect the CLB function while detecting the X1 line resources.(3)A method for configuration testing of metal interconnect wire doubling resources is proposed in this thesis.Based on the proposed metal interconnect wire model,by combining the concept of depth first search algorithm and heuristic search algorithm in graph theory,we generate a high coverage configuration test graph for metal interconnect double line resources under fewer test configurations.This method can achieve automatic search path and automatic generation of test configuration for internal interconnection structure,and get as small as possible configuration times,can better shorten the time cost of testing.(4)By study the common fault models of FPGA,and the corresponding test vectors are studied for the fault models of metal interconnect wire.The failure models of metal interconnect wire are effectively detected,and the validity of the configuration graph is verified by testing vectors on the test platform.