Superscalar Out-of-order Processor Steady State Throughput Modeling

With the rapid development of processor technology,the evaluation of processor performance has gradually become the focus in the academic and industrial circles.In the evaluation of the superscalar out-of-order processors' performance,the steady state performance part accounts for about 20% of the total performance.Currently,the steady state throughput model based on the instruction window curve is widely used to evaluate the steady state performance of the processor,but this model lacks the comprehensive consideration of instruction dependency and instruction type,and there is an unreasonable assumption in the model: the size of the instruction window is equal to the reorder buffer size.In order to evaluate the steady state performance of the processor accurately,this thesis aims to consider the instruction dependency and instruction type together and establishes a steady state throughput model based on the neural network.The work of this thesis mainly consists of two aspects: Firstly,experiments are designed to verify and analyze the related factors affecting the steady state throughput,and the steady state throughput model based on the IW curve is evaluated.The corresponding test benchmarks are designed to verify and analyze effects of the instruction dependency,the instruction mix ratio,the pipeline width and the number of functional units.Then,on the gem5 simulation platform,the steady-state throughput model based on the IW curve is reproduced.Meanwhile,this thesis evaluates and analyzes predecessors' model to point out its shortcomings from two aspects of average instruction stall time and instruction window size.Secondly,a steady state throughput model based on neural networks is established.On the basis of the critical path length theory established by the predecessors,this thesis proposes a new feature named dependence delay distribution and establishes the steady state throughput model based on this feature in software level.Moreover,this thesis modifies and improves the model with considering some micro-architecture related parameters.The model established in this thesis predicts the steady state throughput of eleven different benchmarks under four different ROB configurations respectively.Compared with the simulation results of gem5,the average self-prediction accuracy of the model is about 94.4%.The average accuracy of the model's cross-application forecast is about 91%.Compared with the previous model based on IW curve,the average precision of the model is increased by more than 10%.In terms of time cost,the model can save on average 71.42% of the time compared with the cycle-accurate simulation of gem5.