Automatic Generation Method Of Low-order Models For Analog Integrated Circuits With Applications

Nowadays,analog integrated circuit(IC)design still depends heavily on manual analysis,which greatly impedes the entire SoC design process.As one indispensable part of analog IC design,reliable macromodel for analysis lacks systematic and automatic generation procedure.This thesis discusses the relation between circuit topology and a symbolic method call Graph-Pair Decision Diagram(GPDD).The topological simplification is proposed with an efficient symbolic algorithm for automatic low-order model generation.According to the experimental results,the simplified model matches the original circuits in performance and topology to good agreement.The validity and robustness of proposed method have been verified by circuits with various topologies and sizings extensively.The proposed model generation method has been applied to two scenarios.The first problem is to automatically construct the time-domain model for largesignal analysis,and the typical slew-settling behavior can be captured by the proposed model.The other one is to analyze common mode rejection ratio(CMRR)and power supply rejection ratio(PSRR)with symbolic calculation and sensitivity analysis under multi-port construction.In the thesis,relevant test results and algorithm performance are provided.