Design And Research For CNFET-based Last Level Cache

The memory wall is a key issue to limit the performance of processor.And the last-level cache(LLC)with the largest capacity of on-chip cache is one of the most significant factors to affect the performance of processor.In recent years,the Moore's Law of COMS is no longer extended.The carbon nanotube field effect transistors(CNFET)emerges as a promising alternative to the conventional CMOS for the much higher speed and power efficiency.However,there are serious process variations(PV)in the manufacturing process of CNFETs,which bring huge performance loss to CNFET-based caches.This thesis develops a complete solution for the PV of the CNFET-based LLCs to maximize the potential benefits of itFirstly,for the two typical layouts of LLC(CNT parallel to wordline and CNT parallel to bitline),this thesis utilizes the asymmetry of access latency to proposes the variable aware Set(VAS)LLC and variable aware Way(VAW).For VAS LLC,this thesis proposes a static page mapping strategy to ensure that the most frequently used virtual pages are mapped to fast partition of LLC.Similarly,for VAW LLC,this thesis proposes a latency-aware LRU replacement strategy to assign the most recently used data to the fast cache way.The experimental results show that the performance of LLC with the optimized method is improved by 39% on average and the power consumption is reduced by 10% on average,compared with the traditional CNFET LLC.Secondly,this thesis proposes a solution to the PV for the CNFET-based non-uniform cache access(NUCA)LLC.For the static non-uniform cache access(S-NUCA),this thesis provides the bank aware static non-uniform cache access(BA-SNUCA),the each bank of the BA-SNUCA is a variable aware cache.The experimental results show that the IPC of the on-chip system with BA-SNUCA can improve 7.5% and the power consumption can reduce 6.8%,compared with the traditional S-NUCA.For dynamic non-uniform cache access(D-NCUA),this thesis proposes a latency-aware migration strategy which can mitigate the frequently used data towards the fast banks.The experimental results show that the IPC of on-chip system with the latency-aware D-NCUA can increase 5.9% on average and the power consumption can cut down 5.3%,compared with the traditional gradual promotion migration strategy.