Algorithm And Hardware Architecture For Polar Codes Decoder

Polar codes are the first forward-error-correction codes that have been proved to be able to achieve the channel capacity of binary discrete memoryless channels,when the block-length tends to infinity.The fundamental decoding algorithm of polar codes is successive-cancellation(SC)whose complexity is lower than that of other modern error-correction codes,such as low-density parity-check codes and Turbo codes.Duo to their excellent performance and low-complexity encoding/decoding processes,polar codes have been adopted as one of the channel coding scheme in the upcoming fifth generation mobile communication systems.The SC flip(SCF)decoding algorithm offers a better error-correction performance than the SC decoding algorithm.To reduce the decoding latency,the fast simplified SC(Fast-SSC)decoding is merged with the SCF decoding,resulting in the Fast-SSC-Flip decoding algorithm.In this paper,a new Fast-SSC-Flip decoding algorithm is presented.A novel decision LLR calculation method and bit-flipping scheme in single-parity-check nodes are presented,leading to a better error-correction performance than the prior art.Besides,more types of special nodes in the decoding tree are considered in the proposed algorithm to further reduce the decoding latency.Moreover,this paper proposes an improved Fast-SSC-Flip decoding algorithm,which aims to flip the first error of invalid codewords to improve the performance of polar codes.Compared with the prior art,this decoding algorithm has about 0.45 dB performance gain.For most of undecodable codewords under the Fast-SSC decoding,the improved Fast-SSC-Flip decoding can successfully decode them much faster than the prior art.The error-correction performance of existing soft-output decoding algorithms of polar codes is unsatisfactory.To address this issue,this paper proposes two novel soft-cancellation flip(SCAN-Flip)decoding algorithms,named LLR based SCAN-Flip and new metric based SCAN-Flip,respectively.Simulation results show that these two algorithms can substantially meliorate the error-correction performance while share a similar complexity to the original SCAN.Based on the Fast-SSC decoding algorithm,this paper proposes an efficient de-coder architecture.Well-optimized components in the decoder core are developed,their advantage is that the critical path is very short.Additionally,several efficien-t approximate computing units(Apx-CUs)are introduced to substitute their accurate counterparts in the decoder to achieve even higher operating frequency.FPGA imple-mentation results show that this design is about 1.5times faster than the prior art,and the proposed Apx-CUs can bring additional 19%processing speed.