The Design And Research Of Structure Which Is Lateral Superjunction MOS Devices

Because of its convenient transmission,convenient transformation,and no pollution,electric energy plays a decisive role in the development of human society.However,these devices cannot use electrical energy directly,but need to convert electrical energy through power semiconductor devices.Among them,power MOS devices are widely used because of their advantages such as high input impedance,ease of driving,and high frequency.However,the BV and Ron,sp of MOS devices are strongly constrained by the doping concentration of the drift region,and therefore there is an inherent contradiction("Silicon Limit"Ron,sp?BV2'5).In order to solve this contradiction,the super-junction structure was proposed.The important relationship of the power MOS Ron,sp?BV2 5 is reduced to 1.32,making it a "milestone for power MOS devices".When superjunction structure is applied to LDMOS,it is affected by a substrate assisted depletion effect(SAD),thereby reducing the device's BV.In order to eliminate the SAD effect,based on the equivalent substrate model theory,this paper proposes two novel device structures for bulk silicon and SOI substrates from the perspective of optimizing the charge compensation layer(CCL).The simulation software which was used to design two kinds of device structures and carry out simulation analysis of electrical characteristics.(1)A novel superjunction(SJ)lateral double-diffused MOS(LDMOS)with Segmented Buried P-layer(SBP)is proposed.SBP SJ LDMOS introduces segmented buried P-layer between the drift region and the substrate.The buried layer with gradual length from the source to the drain of SBP SJ LDMOS can also optimize the charge distribution of the drift region,which means it will reduce the charge compensation for SJ layer caused by the drift region under the source and increase the charge compensation for SJ layer caused by the drift region under the drain,thus achieving charge balance in the SJ layer.Compared with the conventional(Con.)SJ LDMOS at the same drift region of 33.5?m,the breakdown voltage(BV)of the SBP SJ LDMOS is 680.5V,enhanced by 41.7%.In addition,P-layer can also assist in depleting drift region to increase the concentrate of drift region and to decrease the Ron,sp of the device.When the gate voltage is 15V,the Ron,sp is 42.8 m?· cm2,reduced by 20.5%and the figure-of-merit(FOM)is 10.8MW·C cm-2,increased by 152.8%.Finally,the design of layout and the process preparation scheme for the SBP S J LDMOS are performed.(2)A novel superjunction(SJ)LDMOS with steps buried oxide(SBOX)is proposed.The feature of the device is that the SBOX in the SJ LDMOS based on the Enhanced Dielectric Field(ENDIF)is designed.The drift region is divided into three parts according to the depths of the SBOX that gradually increased from source to drain,which will optimize the drift region charge distributions and shield the substrate assisted depletion effect(SAD),Thus the SJ will reach the charge balance and increase the lateral breakdown voltage(BV)of the device.Furthermore,the SBOX can also fix holes so that the hole concentrations of SBOX upper interface is greatly increased,which will increase the vertical electric field.Therefore,the BV of device is increased and the tradeoff between the BV and specific on-resistance(Ron,sP)is achieved.Compared with the conventional SOI SJ LDMOS(Con.SOI SJ LDMOS)at the same 14 ?m drift region length,the BV of the SBOX SJ LDMOS is increased from 207.1 V to 296.9 V and the figure of merit(FOM)is enhanced from 4.5 MW· cm-2 to 9.9 MW·Cm-2.Finally,according to the structural characteristics of SBOX SJ LDMOS devices,the process flow and layout are designed.