Research Of 3D Optical And Electrical Hybrid Network On Chip Architectures

With the rapid development of high-performance computing,big data,and artificial intelligence,demand of the computing ability of the chip is increasing.The bottleneck of single-core processors in frequency and temperature has become increasingly prominent.It is an inevitable trend that multi-core processors with higher performance will be achieved at a lower frequency.However,with the increasing number of processor cores integrated on a single chip,in network on chip(NoC),the shortcomings such as high latency and high power consumption will limit the performance of multi-core processors.The low latency,high bandwidth,and low power consumption of optical interconnects make optical network on chip(ONoC)a new research hotspot.However,the number of waveguide crossings,communication distance,and chip area of the traditional two-dimensional ONoC limit the scalability of the network on chip.Three-dimensional integration technology is a promising solution for two-dimensional optical network by transforming one network layer into a multilayer network.This thesis summarizes the research progress of 3D optoelectronic hybrid architectures and presents solutions to existing problems.Firstly,we studied the switching mechanism of network on chip.In circuit switched optical network on chip,once an output port of router is occupied during the reservation of the optical path,the set-up packet will wait in the current node until the desired port is released.The currently blocked packets will further block other packets.This situation greatly reduces the link utilization and the blocking will spread to the whole network soon,thereby degrading the network delay and throughput performance.To solve this problem,we propose a communication method called HTRM.This method employs a new joint metric of predict time and the number of blocking packets.Rules are defined according to the new metric for the setup packet,thus increasing the link utilization.Simulations show that the network latency of HTRM is reduced by at least 40% and the throughput HTRM is increased by 30% under the synthetic traffic model compared with those of the traditional communication method.Under real application traffic,the acceleration speed of HTRM is increased by 5%.Secondly,we studied three-dimensional on-chip networks with large-scale nodes.Excellent performance of on-chip multi-core systems require the support of excellent architecturals.Although the HTRM communication method can improve the performance to some extent,it still cannot solve the problems of long distance,high delay,and excessive loss of the communication process when the network scale is expanded.To this end,we designed a low-latency,low-loss 3D opto-electronic hybrid on-chip network architecture,Venus.Combining wavelength routing technology and three-dimensional integration technology,the communication distance of each two nodes is only one hop,and two nodes in any different subnet realize non-blocking communication,thereby reducing the average end-to-end communication of the on-chip network.By using multiple ring structures and designing an optical network interface among the rings,we reduced the number of waveguide crossings and the number of micro-rings on the critical path,thus reducing optical signal loss and crosstalk.The simulation results show that on the scale of 1000 cores,the designed 3D opto-electronic hybrid on-chip network architecture has a 75.3% lower average latency,77.9x throughput,and the worst insertion loss reduced by 64.2% compared with the network based on the 3D mesh structure.compared with state of the art network architecture,the average latency and throughput are almost equal,and the worst insertion loss is reduced by 40.1%.Finally,we studied the 3-D on-chip network for special applications.Venus has excellent performance under the 1000-core nodes.However,Venus also has some common problems which are the intrinsic defects of the general-purpose network architectures.First,Venus has poor performance in multicast traffic.Second,the network bandwidth of Venus is symmetrical.In some asymmetric traffic applications,network performance will become worse.However,in recent years,the two points of flow characteristics have been generated in the implementation of neural network applications.Therefore,we propose a three-dimensional heterogeneous hybrid on-chip network,called CHNoC,for large-scale convolutional neural networks.Using opto-electrical hybrid interconnection to map different convolutional neural network layers with different bandwidth requirements to different hardware layers,and to use the targeted asymmetry of design and hierarchical interconnection in convolutional neural networks to increase bandwidth utilization rate.