Research On The Implementation Method Of Spinal Decoder

In the field of wireless communication,people pay more and more attention to improving the reliability and efficiency of information transmission.The technology of wireless communication is developing rapidly.The rateless coding method provides a new direction for wireless communication research.Essentially,the rate of rateless codes can be adjusted automatically according to the channel state.The rateless coding technique has many advantages such as reliability,speed and efficiency.Spinal code is a kind of rateless codes that can be applied to the wireless communication environment.Spinal code uses the hash function to generate pseudo random sequences as long as possible.The coding structure of Spinal code is relatively simple.It can adapt to the specific state of the channel and has excellent rate performance.In binary symmetric channel and additive gaussian white noise channel,Spinal code can obtain the rate performance of access to channel capacity.In this thesis,the realization method of Spinal decoder is studied.Firstly,the FPGA implementation of Spinal coding algorithm is designed.Then the FPGA implementation of Bubble decoding algorithm and the forward stack decoding(FSD)algorithm of Spinal code are designed.In the traditional Bubble decoder,the path selection network structure adopts the bitonic sorting algorithm to realize the deletion of nodes.In order to improve the throughput of the Bubble decoder and reduce the resources assumption,this thesis presents the combined selection as an optimization method for the path selection network in the Bubble decoder.A path selection method based on combined selection is proposed,and the combined selection network structure and the bitonic combination network structure are given.The designed structure can effectively avoid the large time delay problem caused by bitonic sorting algorithm and improve the decoding speed.Compared with the traditional scheme,the Bubble decoder based on the combined selection network structure not only reduces the consumption of hardware resources,but also improves the decoding speed.The throughput can reach 19.6Mbps.The bitonic combination network structure can increase the decoding speed of the Bubble decoder,and the throughput can reach 21.0Mbps.The FSD algorithm is another kind of decoding method of Spinal code.The FSD algorithm can not only obtain good rate performance,but also have lower computational complexity than the Bubble decoding algorithm.In this thesis,the stack-bucket algorithm is applied to the FSD algorithm.And a FPGA implementation method of Spinal code FSD algorithm is proposed based on stack-bucket algorithm.Combined with the realization of the Bubble decoding algorithm,the FPGA implementation of Spinal code FSD algorithm is completed.The forward stack decoder takes up less hardware resources,and has higher decoding speed.The throughput can reach 25.2Mbps.