Research And Development Of A High Throughput Slot Schedule Algorithm Based On Distributed TDMA Protocal

With the rapid development of communication technology,wireless ad hoc networks due to its features of no center,fast networking and distributed control,has been increasingly widely used in civil and military,rescue and other fields.Besides the common data service,those multimedia services with greater bandwidth and stricter delay requirements needs to be carried in ad hoc networks.Due to its high throughput capability,TDMA protocols are suitable to broadband wireless ad hoc networks.Therefore,how to further improve the network throughput has become a key problem in the research and development of the MAC protocols in wireless ad hoc networks.Wireless ad hoc network equipment generally adopts a layered design and development method,but the mutual influence between the protocol design of various layers in the implementation is often ignored,as a result,a more optimized system design cannot be realized.There is a large processing delay in the complex data process of the physical layer,which has a great influence on the design of the TDMA protocol of the MAC layer.The traditional TDMA protocol of the MAC layer in ad hoc networks is often not designed in conjunction with the physical layer.This thesis considers Xilinx xc7z030 FPGA chip as the main of hardware development platform of the wireless ad hoc networks,firstly analyzes the impact of the physical layer on the TDMA protocol design of the MAC layer in the software layered development.And combined with a large processing delay in the physical processing layer,this thesis analyzes the advantages and disadvantages of a variety of ARQ protocols of the link error technology.Then,based on the above analysis and combined with the characteristics of the physical layer,this thesis presents the design of the TDMA protocol of the MAC layer.It adopts a superframe structure divided by 4+4 timeslot groups,and based on this superframe structure,the time-slot-based link error control method and the time slot scheduling algorithm are designed.The time-slot-based link error control method is further used to improve the utilization of time slots,and the time slot group-based time slot scheduling algorithm is used to guarantee the the efficiency and flexibility performance of data scheduling,and as a result,the design greatly promotes the throughput of the network.Then,the function of the algorithm is simulated and verified by ISE Simulator software.The simulation results show the feasibility and correctness of the algorithm.Finally,a variety of scenarios are tested on the hardware development platform,including multi-node network test,Ping packet test and throughput test,and video transmission test in the network.The results of these tests verify the feasibility and the correctness of the design.In order to compare with another set of system software in the MAC protocol using stop-and-wait ARQ design,a comparative test of network throughput on the same development platform is conducted,the actual test results show that the design of this thesis is even better in terms of network throughput performance.