Research Of The TDS-OFDM Synchronization Technology On The High Speed Power Line Communication

Currently,power line communications?PLCs?have become the research hotspot due to low cost of laying,easy access implementation and wide coverage.But they still have some disadvantages,such as high modulation complexity,poor synchronous performance and so on.To solve the above problems,the optimized carrier and the timing recovery schemes,under the time domain synchronous orthogonal frequency division multiplexing?TDS-OFDM?modulation,are researched in this dissertation.Firstly,the current research status,development and common modulation schemes of the PLC are briefly introduced.Secondly,the existing PLC channels model,the shortcomings of traditional carrier and symbol timing recovery schemes are analyzed emphatically.Then the optimized TDS-OFDM modulation scheme and its efficient synchronous technologies are proposed to improve the transmission performance of the PLC system.Finally,the innovations of the structure of the synchronous head of the TDS-OFDM frames,symbol timing loop filter coefficients and some other parameters,the parallel processing and maximum a posterior probability?MAP?timing estimation are carried out in the PLC system.The main content and contributions of this dissertation are listed as follows.1.To improve the problems of large link loss,low transmission signal to noise ratio?SNR?and difficulty to increase transmit power in the PLC system,which will lead to low efficiency,the TDS-OFDM modulation scheme is studied.Firstly,the application characteristics of the OFDM modulation in the complex PLC channels are analyzed.Secondly,the optimized synchronous scheme of the TDS-OFDM system is proposed with simulation of the PLC channels.Then the qualitative and quantitative analysis is completed for its transmission performance and computational complexity.Finally,the analysis results show that TDS-OFDM modulation scheme and its synchronous technologies are adopted in the PLC system,which can eliminate the influence of the high noise,multipath fading,and effectively improve the spectrum utilization.2.To overcome the higher computational complexity,in the current PLC system,an improved frequency offset scheme with low complexity is proposed by improving the structure of the TDS-OFDM frame.Firstly,a frame head is constructed by using five segments pseudo-random noise sequence?PN?.And the first sequence is the same as the fourth sequence,as well as the relationship of the second and the fifth one.Secondly,five segments sequence are ordered to synthesize the same sequence of three segments.Finally,the frequency offset estimation can be achieved by taking one of the three segments sequence to complete autocorrelation.The simulations indicate that,when the length of the frame head is the same,the performance of the proposed algorithm is better than the existing cyclic prefix?CP?and PN algorithms with about 5dB and 1dB SNR performance gains,at BER of 10^-4,respectively.In addition,when the length of the frame head and the autocorrelation sequence are 420 and 165 separately,the number of correlations is reduced by 1185 times,compared with the existing PN algorithm.In summary,the proposed scheme can not only reduce the complexity of frequency offset estimation,but also help to improve the quality of PLC transmission.3.To improve the accuracy and processing problems of symbol timing recovery in the PLC system,under the MAP estimation criterion,an improved low complex timing recovery scheme is proposed by using the parallel interpolation method,with the high efficiency.Firstly,this scheme mainly uses Lagrange polynomial parallel interpolation to get the amplitude and polarity change information of symbol sampling points.Then the location of the best sampling points and timing error detection can be finished.Secondly,the filter coefficients are calculated by the loop bandwidth,gains and some other parameters to affect the output,and then control the interpolation.Finally,the error estimation accuracy is further estimated by combining the filter output with the MAP criterion.The simulation results indicate that,the SNR performances of the proposed algorithm are improved about 2dB,4dB and 6dB compared with the existing MAP,Gardner and MM algorithms,at BER of10^-3,respectively.Moreover,the mean square error?MSE?curve is almost coincident with the superior MAP algorithm,approaching the Cramer-Rao bound.In addition,the parallel processing can also speed up the running rate of the system.The actual time consumption is only 1/4 of the serial processing with 4 parallel branches.By the optimization of the modulation and the corresponding synchronous schemes,the performance of the PLC system can be greatly improved with low processing complexity.Therefore,it possesses rather high engineering application value and can be widely used in the practical PLC systems,especially in the IoT systems and so on.